Transcription of Summary of Verilog Syntax - Electrical Engineering Faculty
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Summary of Verilog Syntax - Electrical Engineering Faculty
Copyright 1997, Hon-Chi Ng. Permission to duplicate and distribute this document is herewith granted for sole educational purpose without any commercial advantage, provided this copyright message is accompanied in all the duplicates distributed. All other rights reserved. All Cadence s tools referred are trademarks or registered trademarks of Cadence Design Systems, Inc. All other trademarks belong to their respective owners. Summary of Verilog Syntax 1. Module & Instantiation of Instances A Module in Verilog is declared within the pair of keywords module and endmodule. Following the keyword module are the module name and port interface list.
Cpr E 305 Laboratory Tutorial Verilog Syntax Page 2 of 2 Last Updated: 02/07/01 4:24 PM module my_module ( a, b, c, d ); parameter x = 0;
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