Transcription of System Generator for DSP - Xilinx
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System Generator for DSP - Xilinx
System Generator for DSPG etting Started GuideUG639 (v ) October 16, 2012 This document applies to the following software versions: ISE Design Suite through document applies to the following software versions: ISE Design Suite through document applies to the following software versions: ISE Design Suite through document applies to the following software versions: ISE Design Suite through Generator for DSP Getting Started (v ) October 16, 2012 Xilinx is disclosing this user guide, manual, release note, and/or specification (the "Documentation") to you solely for use in the development of designs to operate with Xilinx hardware devices.
System Generator includes a FIR Compiler block that targets the dedicated DSP48 hardware resources in the Virtex®-4 and Virtex-5 devices to create highly optimized implementations that can run in excess of 500 Mhz. Configuration options allow generation of direct, polyphase decimation, polyphase interpolation and oversampled implementations.
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