Transcription of The Delay-Locked Loop
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The Delay-Locked Loop
A C ircu it for All Seasons Behzad Razavi The Delay-Locked Loop D. Delay-Locked loops (DLLs) can be considered as feedback circuits that phase lock an output to an input without the use of an oscillator. In some applications, DLLs are neces- to adjust the delay and force DT. toward zero. This conjecture leads us to the arrangement depicted in Fig u r e 2(c). He r e , a phase detector mea- of the phase/frequency detector (PFD), charge pump (CP), and capacitor pro- vides an infinite gain, thus driving the skew toward zero. The variable- delay stage is sary or preferable over phase- locked sures the skew and The origins of realized as a voltage- loops (PLLs), with their advantages adjusts t he delay of DLLs can be controlled delay line including lower sensitivity to supply B 2 t o r e d u c e DT.
phase noise of a delay line, S z,DL, and that of a ring oscillator using such a line, S z,ring, are related as follows: Sf S , f f,,ring 0 2 zz = DL cm rD (5) where f 0 is the oscillation frequency (Figure 6). We conclude that the ring produces much higher phase noise. One interpretation of this result is that, in a ring, an edge continues
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