Transcription of The Delay-Locked Loop
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The Delay-Locked Loop
A C ircu it for All Seasons Behzad Razavi The Delay-Locked Loop D. Delay-Locked loops (DLLs) can be considered as feedback circuits that phase lock an output to an input without the use of an oscillator. In some applications, DLLs are neces- to adjust the delay and force DT. toward zero. This conjecture leads us to the arrangement depicted in Fig u r e 2(c). He r e , a phase detector mea- of the phase/frequency detector (PFD), charge pump (CP), and capacitor pro- vides an infinite gain, thus driving the skew toward zero. The variable- delay stage is sary or preferable over phase- locked sures the skew and The origins of realized as a voltage- loops (PLLs), with their advantages adjusts t he delay of DLLs can be controlled delay line including lower sensitivity to supply B 2 t o r e d u c e DT. A s traced to a paper (VCDL). Figure 2(e). noise and lower phase noise. This with PLLs, the low-pass published shows an example of article deals with fundamental DLL filter attenuates the in 1961.
to adjust the delay and force DT toward zero. This conjecture leads us to the arrangement depicted in Figure 2(c ). Here, a phase detector mea-sures the skew and adjusts the delay of B 2 to reduce DT. As with PLLs, the low-pass filter attenuates the high-frequency compo-nents generated by the PD. This circuit exemplifies a simple delay-locked loop.
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