Transcription of TUTORIAL CADENCE DESIGN ENVIRONMENT
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TUTORIAL CADENCE DESIGN ENVIRONMENT
TUTORIAL . CADENCE DESIGN . ENVIRONMENT . Antonio J. Lopez Martin Klipsch School of Electrical and Computer Engineering New Mexico State University October 2002. CADENCE DESIGN ENVIRONMENT SCHEDULE CADENCE SEMINAR. MONDAY, OCTOBER 21. 9:00H-9:30H. Lecture Introduction to CADENCE . Basic Features 9:30H-11:00H: Lecture Schematic Edition and Circuit Simulation with CADENCE DFWII. 11:00H-11:15H: Break 11:15H-13:00H: Lab session Schematic Edition and Simulation of an OTA. TUESDAY, OCTOBER 22. 9:00H-11:00H. Lecture Layout Edition and Verification with CADENCE Virtuoso and Diva. 11:00H-11:15H: Break 11:15H-13:00H: Lab session Layout of an OTA. Verification: DRC, LVS, post-layout simulation (First session).
vendors (e.g., HSPICE) if they are installed and licensed. Once circuit specifications are fulfilled in simulation, the circuit layout is created using the Virtuoso Layout Editor. The resulting layout must verify some geometric rules dependent on the technology (design rules). For enforcing it, a Design Rule Check (DRC) is performed. Optionally ...
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