Transcription of TUTORIAL CADENCE DESIGN ENVIRONMENT - Anasayfa
{{id}} {{{paragraph}}}
Example: bankruptcy
TUTORIAL CADENCE DESIGN ENVIRONMENT - Anasayfa
TUTORIAL . CADENCE DESIGN . ENVIRONMENT . Antonio J. Lopez Martin Klipsch School of Electrical and Computer Engineering New Mexico State University October 2002. CADENCE DESIGN ENVIRONMENT SCHEDULE CADENCE SEMINAR. MONDAY, OCTOBER 21. 9:00H-9:30H. Lecture Introduction to CADENCE . Basic Features 9:30H-11:00H: Lecture Schematic Edition and Circuit Simulation with CADENCE DFWII. 11:00H-11:15H: Break 11:15H-13:00H: Lab session Schematic Edition and Simulation of an OTA. TUESDAY, OCTOBER 22. 9:00H-11:00H. Lecture Layout Edition and Verification with CADENCE Virtuoso and Diva. 11:00H-11:15H: Break 11:15H-13:00H: Lab session Layout of an OTA. Verification: DRC, LVS, post-layout simulation (First session). WEDNESDAY, OCTOBER 23. 9:00H-11:00H. Lecture Advanced Layout DESIGN Transfer to foundry Case study: a commercial IC designed with CADENCE .
Now we are going to illustrate how to carry out the complete design flow shown in Fig. 1 using the Cadence tools. A simple Operational Transconductance Amplifier (OTA) will be designed in the AMI 0.5µm CMOS technology. However, the same procedures apply to complete chip designs. 5.1. Library creation and selection of technology
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: