Transcription of UDA1334ATS Low power audio DAC with PLL - NXP
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UDA1334ATS Low power audio DAC with PLL - NXP
DATA SHEETP roduct specificationSupersedes data of 2000 Feb 092000 Jul 31 INTEGRATED CIRCUITS UDA1334 ATSLow power audio DAC with PLL2000 Jul 312 NXP SemiconductorsProduct specificationLow power audio DAC with format data digital audio system clock generation2 APPLICATIONS3 GENERAL DESCRIPTION4 ORDERING INFORMATION5 QUICK REFERENCE DATA6 BLOCK DIAGRAM7 PINNING8 FUNCTIONAL stream interface format control9 LIMITING VALUES10 HANDLING11 THERMAL CHARACTERISTICS12 QUALITY SPECIFICATION13DC CHARACTERISTICS14AC INFORMATION16 PACKAGE to soldering surface mount of surface mount IC packages for wave and reflow soldering methods18 DATA SHEET STATUS19 DISCLAIMERS2000 Jul 313 NXP SemiconductorsProduct specificationLow power audio DAC wi
In audio mode, pin SYSCLK/PLL1 is used to set the sampling frequency range as given in Table 1. Table 1 Sampling frequency range in audio mode 8.1.2 VIDEO MODE In video mode, the master clock is a 27 MHz external clock (as is available in video environment). A clock-out signal is generated at pin DEEM/CLKOUT. The output frequency
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