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UltraScale Architecture Clocking Resources User …
UltraScale Architecture Clocking ResourcesUser Guide UG572 ( ) April 9, 2018 UltraScale Architecture Clocking Resources2UG572 ( ) April 9, HistoryThe following table shows the revision history for this VersionRevision04/09 2: Updated the BUFG_GT and BUFG_GT_SYNC 3: In Table 3-4, updated note 3: In Table 3-4, updated the description of BUF_IN for the COMPENSATION attribute on page 2: Updated the discussion on page 15. Added clarification to the BUFG_GT and BUFG_GT_SYNC 3: Updated the Dynamic Phase Shift Interface in the MMCM section. Added Table 3-6 and Table 3-8. In Table 3-12, updated the descriptions for CLKOUT[0:1]_PHASE and 1: Updated the discussion on page 9 about the differences between clock capable and global clock 2: Added clarification to the Global Clock Inputs section. Added further information following Figure 2-3. Updated the BUFGCE_DIV section. Revised the BUFG_GT_SYNC description on page 33 to include the UltraScale + 3: Added the UltraScale + device MMCME4 and PLLE4 primitives to the MMCM Primitives and PLL Primitives sections.
UltraScale Architecture Clocking Resources 5 UG572 (v1.7) April 9, 2018 www.xilinx.com Chapter1 Overview Introduction to UltraScale Architecture The Xilinx® UltraScale™ architecture is a revolutionary approach to creating programmable
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