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UltraScale Architecture Configurable Logic Block User ...
UltraScale Architecture Configurable Logic Block user Guide UG574 ( ) February 28, 2017. Revision History The following table shows the revision history for this document. Date Version Revision 02/28/2017 Changed Dual-port 32 x (1 to 4)-bit RAM to Dual-port 32 x (1 to 8)-bit RAM and Quad-port 32 x (1 to 8)-bit RAM to Quad-port 32 x (1 to 4)-bit RAM under Distributed RAM (SLICEM Only). Clarified second paragraph following Figure 5-5. Deleted the word interposer preceding boundaries and connections under Second Generation 3D IC Interconnect. 11/24/2015 Added UltraScale + device information. 10/29/2015 Deleted last bullet under Differences from Previous Generations. Updated Figure 2-1. Updated last paragraph under Multiplexers and first paragraph under 32:1. Multiplexer. Updated second paragraph under Distributed RAM (SLICEM Only). 02/20/2015 Changed title of Chapter 1, from Introduction to Overview . Added last two sentences to CLB Slice Resources. Clarified first paragraph under CLB Resources and changed Quad-port 32 x (1 to 4)-bit RAM to Quad-port 32 x (1 to 8)-bit RAM and Dual-port 128 x 1-bit RAM to Dual-port 128 x 2-bit RAM under Distributed RAM.
[Ref 1]. Each 6-input LUT can implement a 4:1 multiplexer (MUX). Dedicated multiplexers in the slices combine the LUTs together to create ev en wider functions without having to connect to another slice. All the LUTs in a slice can be combined together as a 32:1 MUX in one level of logic. X-Ref Target - Figure 1-1 Figure 1-1: LUT Configurations
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