Transcription of UltraScale Architecture Configuration User Guide
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UltraScale Architecture Configuration User Guide
UltraScale Architecture ConfigurationUser Guide UG570 ( ) July 28, 2020 UltraScale Architecture Configuration2UG570 ( ) July 28, HistoryThe following table shows the revision history for this VU57P device to Ta b l e 1 - 3, added KU19P, VU23P, and VU57P devices to Ta b l e 1 - 4 and Ta b l e 1 - 5. Updated Ta b l e 8 - 4 descriptions for R_DIS_USER, R_DIS_SEC, and R_DIS_RSA. Updated Ta b l e 9 - 1 5 description for Configuration word 30026001. Added information for encrypted bitstreams using an obfuscated key with the JTAG, SelectMAP, or ICAP VU19P production IDCODE revision to Ta b l e 1 - 5. Updated value for GLUTMASK_B in Ta b l e 9 - 2 coverage of Virtex UltraScale + VU19P, VU47P, and VU49P devices. Updated production IDCODE revisions for Virtex UltraScale + FPGAs in Ta b l e 1 - 5. Updated descriptions for INIT_B and DONE in Ta b l e 1 - 9. Updated Figure 9-4 and Figure 9-13. Added information to SEU Detection and Correction in Chapter coverage of Virtex UltraScale + VU27P and VU29P devices.
processing. Integrating an Arm®-based system for advanced analytics and on-chip programmable logic for task acceleration creates unlimited possibilities for applications including 5G Wireless, next generation ADAS, and Industrial Internet-of-Things. This user guide describes the UltraScale archit ecture-based FPGAs configuration and is part
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