Transcription of UltraScale Architecture DSP Slice User Guide
{{id}} {{{paragraph}}}
Example: tourism industry
UltraScale Architecture DSP Slice User Guide
UltraScale Architecture DSP Slice User Guide UG579 ( ) September 20, 2019. Revision History The following table shows the revision history for this document. Date Version Revision 09/20/2019 Added VU19P, VU45P, and VU47P to Table 1-2. 05/14/2019 In Device Resources, updated Tcl command and added note. In Table 1-2, updated total column for VU11P and VU13P, and added VU27P, VU29P, VU31P, VU33P, VU35P, and VU37P devices. 06/04/2018 Added description of ALUMODE after Figure 5-3, and added Table 5-1. Updated ALUMODE settings in Adder/Subtracter-only Operation. 04/05/2018 In Figure 2-2, connected upper input of INMODE[4]-controlled multiplexer in B input path to configured output selection after B2 stage. 10/18/2017 Added output of P/C multiplexer in Figure 1-1. Added sentence about cascading across clock regions in paragraph after Figure 1-2. Updated X multiplexer inputs in list after Equation 2-1.
The DSP slice in the UltraScale architecture is defined using the DSP48E2 primitive and the slice is referred to as either DSP or DSP48E2 in the Xilinx tools. The basic functionality of the DSP48E2 slice is shown in Figure 1-1. For complete details, refer to …
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: