Transcription of UltraScale Architecture DSP Slice User Guide - Xilinx
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UltraScale Architecture DSP Slice User Guide - Xilinx
UltraScale Architecture DSP Slice User Guide UG579 ( ) September 20, 2019. Revision History The following table shows the revision history for this document. Date Version Revision 09/20/2019 Added VU19P, VU45P, and VU47P to Table 1-2. 05/14/2019 In Device Resources, updated Tcl command and added note. In Table 1-2, updated total column for VU11P and VU13P, and added VU27P, VU29P, VU31P, VU33P, VU35P, and VU37P devices. 06/04/2018 Added description of ALUMODE after Figure 5-3, and added Table 5-1. Updated ALUMODE settings in Adder/Subtracter-only Operation. 04/05/2018 In Figure 2-2, connected upper input of INMODE[4]-controlled multiplexer in B input path to configured output selection after B2 stage.
High-Level Synthesis webpage on page 50 and in Appendix A. Added reference to UltraScale Architecture Libraries Guide (UG974) on page 51. Added reference to UltraScale device data sheets on page 60. Added reference to Vivado High-Level Synthesis, DSP Solution, Vivado Video Tutorials, and Xilinx DSP Training web pages
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