Transcription of UltraScale Architecture DSP Slice User Guide - xilinx.com
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UltraScale Architecture DSP Slice User Guide - xilinx.com
UltraScale Architecture DSP Slice User Guide UG579 ( ) September 20, 2019. Revision History The following table shows the revision history for this document. Date Version Revision 09/20/2019 Added VU19P, VU45P, and VU47P to Table 1-2. 05/14/2019 In Device Resources, updated Tcl command and added note. In Table 1-2, updated total column for VU11P and VU13P, and added VU27P, VU29P, VU31P, VU33P, VU35P, and VU37P devices. 06/04/2018 Added description of ALUMODE after Figure 5-3, and added Table 5-1. Updated ALUMODE settings in Adder/Subtracter-only Operation. 04/05/2018 In Figure 2-2, connected upper input of INMODE[4]-controlled multiplexer in B input path to configured output selection after B2 stage. 10/18/2017 Added output of P/C multiplexer in Figure 1-1. Added sentence about cascading across clock regions in paragraph after Figure 1-2.
UltraScale Architecture DSP48E2 Slice 6 UG579 (v1.9) September 20, 2019 www.xilinx.com Chapter1 Overview Introduction to UltraScale Architecture The Xilinx® UltraScale™ architecture is the first ASIC-class All Programmable architecture
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