Transcription of UltraScale Architecture SelectIO Resources User Guide
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UltraScale Architecture SelectIO Resources User Guide
UltraScale Architecture SelectIO ResourcesUser Guide UG571 ( ) June 12, 2018 UltraScale Architecture SelectIO Resources2UG571 ( ) June 12, HistoryThe following table shows the revision history for this document. DateVersionRevision06/12 1, SelectIO Interface Resources . Updated DQS_BIAS. Starting with Vivado Design Suite , the DQS_BIAS attribute must be set on the port, not on the cell. Added notes that drivers and receivers must be at the same voltage level. Added the last row (OUTPUT_IMPEDANCE) to Table 1-48. Deleted Figure 2-20: COUNT Mode with Fast Updates. Chapter 2, SelectIO Interface Logic Resources . Updated Table 2-4. Clarified reserved bits and defaults in Table 2-39 through Table 3, High Density I/O Resources . Added the ZHOLD heading. Updated DDR Outputs (ODDRE1).02/07 Chapter 2, updated BITSLICE and waveform information.
UltraScale Architecture SelectIO Resources 2 UG571 (v1.13) October 22, 2021 www.xilinx.com Revision History The following table shows the revision history for this document. Date Version Revision 10/22/2021 1.13 Chapter 1: Added description of output-only IOBs to VREF. Updated step 2 in DCI I/O Standard Support. Updated JEDEC specifications in ...
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