Transcription of Understanding High Speed ADC Testing and Evaluation
{{id}} {{{paragraph}}}
Example: biology
Understanding High Speed ADC Testing and Evaluation
AN-835 APPLICATION NOTEOne Technology Way P. O . Box 9106 Norwood, MA 02062-9106, Te l : Fax: Understanding high Speed ADC Testing and Evaluation by Alex Arrants, Brad Brannon and Rob Reeder Rev. B | Page 1 of 28 SCOPE This document describes both the characterization and production test methods used by the high Speed Converter Group of Analog Devices, Inc., to evaluate high Speed analog-to-digital converters (ADCs). While this application note should be considered a reference, it is not a substitute for a product data sheet. DYNAMIC TEST HARDWARE SETUP SNR, SINAD, worst spur, and IMD are tested using a hardware setup similar to that shown in Figure 1. In production tests, the test hardware is highly integrated, but the hardware principles are the same.
voltage regulators j4 clock input filtered analog input logic spi adc n n j6 usb standard usb 2.0 on-board voltage regulators power connector fpga single or multichannel high speed adc evaluation board hsc-adc-evalc clock circuit figure 2. typical hsc-adc-evalc evaluation platform
Loading..
Tags:
Information
Domain:
Source:
Link to this page:
Please notify us if you found a problem with this document: