Transcription of Using Cortex-M3/M4/M7 Fault Exceptions
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Using Cortex-M3/M4/M7 Fault Exceptions
AN209 Using Cortex-M3/M4/M7 Fault Exceptions Copyright 2017 ARM Ltd. All rights reserved Using Cortex-M3/M4/M7 Fault Exceptions MDK Tutorial AN209, Summer 2017, V Abstract ARM Cortex -M processors implement an efficient exception model that traps illegal memory accesses and several incorrect program conditions. This application note describes the Cortex-M Fault Exceptions from the programmers view and explains their usage during the software development cycle. It also contains an example of a HardFault handler that reports information about the underlying Fault . Contents Using Cortex-M3/M4/M7 Fault Exceptions ..1 Abstract ..1 Introduction ..2 Prerequisites ..2 Fault exception handlers ..2 Fault exception numbers and priority ..2 Priority escalation ..3 Synchronous and asynchronous BusFaults ..3 Fault types ..3 Fault exception registers ..4 Control registers for Fault Exceptions ..4 Configuration and Control Register CCR ..5 System Handler Priority Register SHP.
The HardFault exception is always enabled and has a fixed priority (higher than other interrupts and exceptions, but lower than Non-Maskable Interrupt NMI). The HardFault exception is therefore executed in cases where a fault exception is disabled or when a fault occurs during the execution of a fault exception handler.
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