Transcription of Using Cortex-M3/M4/M7 Fault Exceptions
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Using Cortex-M3/M4/M7 Fault Exceptions
AN209 Using Cortex-M3/M4/M7 Fault Exceptions Copyright 2017 ARM Ltd. All rights reserved Using Cortex-M3/M4/M7 Fault Exceptions MDK Tutorial AN209, Summer 2017, V Abstract ARM Cortex -M processors implement an efficient exception model that traps illegal memory accesses and several incorrect program conditions. This application note describes the Cortex-M Fault Exceptions from the programmers view and explains their usage during the software development cycle. It also contains an example of a HardFault handler that reports information about the underlying Fault . Contents Using Cortex-M3/M4/M7 Fault Exceptions ..1 Abstract ..1 Introduction ..2 Prerequisites ..2 Fault exception handlers ..2 Fault exception numbers and priority.
The HardFault exception is always enabled and has a fixed priority (higher than other interrupts and exceptions, but lower than Non-Maskable Interrupt NMI). ... the handler for the new fault cannot preempt the currently executing fault handler.
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