Transcription of VCU118 Evaluation Board - Xilinx
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VCU118 Evaluation Board - Xilinx
VCU118 Evaluation BoardUser GuideUG1224 ( ) October 17, 2018 VCU118 Board User Guide2UG1224 ( ) October 17, HistoryThe following table shows the revision history for this the PCI Express endpoint connectivity list. Added the Electrostatic Discharge Caution section. Updated Callout 25 in Table 2-1. Updated SW16 in Table 2-2. Updated Jumper J7 in Table 2-3. Added Note 1 to Table 2-4. Updated the switch positions in Figure 2-4. Updated the Virtex UltraScale+ XCVU9P-L2 FLGA2104 Device, DDR4 Component Memory, RLD3 Component Memory, and PCI Express Endpoint Connectivity descriptions. Updated the callout locations in the User I/O and CPU Reset Pushbutton sections.
LVDS (U122) SI5335A-B02436-GM, 4 outputs: 300 MHz, 125 MHz, 90 MHz, 33.33 MHz 44 11 System Clock, programmable user clock Si570_0, I2C programmable user clock, 3.3V LVDS (U18) (bottom) with 1-to-2 LVDS MUX/buffer (U157) (top) Silicon Labs SI570BAB0000544DG 2 (default 156.250 MHz) 17
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