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Verilog-AMS Language Reference Manual

verilog -AMSL anguage Reference ManualVersion 30, 2014 AccelleraAnalog and Mixed-signal Extensions to verilog HDLV ersion , May 30, 2014iiCopyright 2014 Accellera Systems Initiative. All rights 2014 Accellera Systems Initiative. All rights Systems Initiative Inc., 1370 Trancas Street #163, Napa, CA 94558, USAV erilog is a registered trademark of Cadence Design Systems, Systems Initiative (Accellera) standards documents are developed within Accellera by itsTechnical Committee. Accellera develops its standards through a consensus development process, approvedby its members and board of directors, which brings together volunteers representing varied viewpoints andinterests to achieve the final product.

Suggestions for improvements to the Verilog-AMS Language Reference Manual are welcome. They should be sent to the Verilog-AMS e-mail reflector v-ams@lists.accellera.org Note: Attention is called to the possibility that implementation of this standard may require use of subject matter covered by patent rights.

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