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VerilogA Reference Manual

verilog -A Reference Manual verilog -A Reference Manual 2 Table of Contents Chapter 1: Introduction .. 6 Analog Modeling .. 6 Hardware Description Languages .. 6 7 7 Conservative Systems .. 8 Natures and 8 Signal Flow 9 Conventions Used in this Document .. 9 Chapter 2: verilog -A 11 Declaring Modules .. 11 Module 11 Ports .. 12 Describing Analog 13 Branches .. 13 Analog 14 Accessing Net and Branch 14 Indirect branch assignment .. 14 Branch Contribution Statement .. 15 Switch Branches .. 15 Hierarchical Structures .. 17 Module Instance Parameter Value Assignment .. 17 By Order .. 17 By Name .. 18 Paramsets .. 18 Ports 21 Port Assignment .. 21 By Order .. 21 Hierarchical system parameters .. 22 23 User-defined Analog 23 Chapter 3: Lexical Conventions .. 26 White 26 26 Operators .. 2 Strings .. 2 Numbers .. 2 Integer Numbers .. 2 Real Numbers .. 3 Scale 3 Keywords .. 4 Identifiers .. 4 Escaped Identifiers.

Verilog-A Reference Manual 7 Verilog and VHDL are the two dominant languages; this manual is concerned with the Verilog language. As behavior beyond the digital performance was added, a mixed-signal language was created to manage the interaction between digital and analog signals. A subset of this, Verilog-A, was defined.

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