VHDL Test Benches - TUT

vhdl Test Benches TIE-50206 Logic Synthesis Arto Perttula Tampere University of Technology Fall 2015 Testbench Design under test Contents Purpose of test Benches Structure of simple test bench Side note about delay modeling in vhdl Better test Benches Separate, better reusable stimulus generation Separate sink from the response File handling for stimulus and response Example and conclusions Lots of miscellaneous self-study material Arto Perttula 2 Introduction Verification is perhaps the most difficult aspect of any design That s not an excuse for omitting it or leaving to Multiple levels: single component, module with multiple sub-components, and system-level Multiple abstraction levels In synchronous design, we verify the functionality at cycle-level accuracy Not detailed timing, which will be checked with static timing analysis (STA) tools Arto Perttula 3 [ } Introductory Question Q: What s the difference between th]

VHDL Test Benches TIE-50206 Logic Synthesis Arto Perttula Tampere University of Technology Fall 2015 Testbench Design under test

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