Transcription of Vitis AI User Guide - Xilinx
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Vitis AI User Guide - Xilinx
Vitis AI User GuideUG1414 ( ) February 3, 2021 Revision HistoryThe following table shows the revision history for this Summary02/03/2021 Version documentUpdated links12/17/2020 Version documentMinor changesDeep-Learning Processor UnitAdded new topics: Alveo U200/U250: DPUCADF8H, AlveoU50/U50LV/U280: DPUCAHX8L, and Versal AI Core Version (vai_q_tensorflow2)Added new sectionPyTorch Version (vai_q_pytorch)Added new topics: Module Partial Quantization, vai_q_pytorch Fast Finetuning, and vai_q_pytorch 5: Compiling the ModelAdded new section: Compiling with an XIR-based 10: Integrating the DPU into Custom PlatformsAdded new A: Vitis AI Programming InterfaceAdded new section: VART Version documentMinor changes07/07/2020 Version document Added Vitis AI Profiler topic.
• Customizes efficient and scalable IP cores to meet your needs for many different applications from a throughput, latency, and power perspective. V i t i s A I T o o l s O v e r v i e w. D e e p - L e a r n i n g P r o c e s s o r U n i t. The Deep-Learning Processor Unit (DPU) is a programmable engine optimized for deep neural networks.
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