Transcription of Vivado Design Suite - Xilinx
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Vivado Design Suite - Xilinx
Vivado AXI Reference [optional] UG1037 ( ) July 15, 2017 [optional] Vivado Design SuiteAXI Reference GuideUG1037 ( ) July 15, 2017 Vivado AXI Reference ( ) July 15, 2017 Revision HistoryThe following table shows the revision history for this document. DateVersionRevision07/15 to match the new Vivado Look and Feel .Updated all IP to reflect current Zynq UltraScale+ MPSoC Processor Device in Chapter AXI SmartConnect IP in Chapter 3, and mention of SmartConnect IP capabilities throughout the AXI Verification IP in Chapter AXI4-Stream Verification IP in Chapter Zynq-7000 AP SoC Verification IP in Chapter Quick Take the AXI IP Catalog Figure 2-1.
AXI Virtual FIFO Controller. DataMover Simulating IP. Using Debug and IP. Performance Monitor IP. AXI BFM. Bus Functional Models. Choosing a Programmable Logic Interface. Zynq-7000 All Programmable SoC Processor IP. MicroBlaze Processor. Added: Migrating to AXI for IP Cores. Migrating to AXI for IP Cores. Migrating HDL Designs to use DSP IP ...
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