Transcription of Vivado Design Suite - Xilinx
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Vivado Design Suite - Xilinx
Vivado AXI reference [optional] UG1037 ( ) July 15, 2017 [optional] Vivado Design SuiteAXI reference GuideUG1037 ( ) July 15, 2017 Vivado AXI reference ( ) July 15, 2017 Revision HistoryThe following table shows the revision history for this document. DateVersionRevision07/15 to match the new Vivado Look and Feel .Updated all IP to reflect current Zynq UltraScale+ MPSoC Processor Device in Chapter AXI SmartConnect IP in Chapter 3, and mention of SmartConnect IP capabilities throughout the AXI Verification IP in Chapter AXI4-Stream Verification IP in Chapter Zynq-7000 AP SoC Verification IP in Chapter Quick Take the AXI IP Catalog Figure 2-1. Updated the IP Project Settings Packaging tab in Figure Features and Limitations in AXI Infrastructure IP Vivado Lab Tools to Vivado Lab Edition throughout the XAPP1231 document reference to additional direct links to AWCACHE and ARCACHE for AXI4-Lite to Signal not present in Appendix A, Write Data Channel Signals and Appendix A, Read Data Channel :IP Interoperability.
Vivado AXI Reference Guide www.xilinx.com 6 UG1037 (v4.0) July 15, 2017 Chapter 1: Introducing AXI for Vivado Xilinx introduced these interfaces in the ISE ® Design Suite, release 12 .3. Xilinx continues to use and support AXI and AXI4 interfaces in the Vivado® Design Suite. Summary of AXI4 Benefits
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