Transcription of XADC Wizard v3 - Xilinx
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XADC Wizard IP Product GuideVivado Design SuitePG091 October 5, 2016xadc-wiz October 5, 2016 Table of ContentsIP FactsChapter 1: OverviewOperating System Requirements .. 6 Feature Summary.. 7 Applications .. 7 Before You Begin .. 8 Installing the Wizard .. 9 Verifying Your Installation.. 9 Licensing and Ordering Information .. 10 Chapter 2: Product SpecificationFunctional Overview .. 11 Standards .. 11 Performance .. 12 Resource Utilization .. 12 Port Descriptions .. 12 Register Space .. 15 XADC Wizard Register Descriptions for AXI4-Lite Interface .. 16 XADC Wizard Local Register Grouping for AXI4-Lite Interface.
The XADC Wizard generates Verilog or VHDL Register Transfer Level (RTL) source code to configure the XADC primitive in Xilinx ® 7 series FPGAs. An example design and simulation test bench demonstrate how to integrate the core into user designs. The XADC Wizard is included with the Vivado® Design Suite. For information about system
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