Transcription of XC2C256 CoolRunner-II CPLD - Xilinx
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XC2C256 CoolRunner-II CPLD - Xilinx
DS094 ( ) March 8, Specification 2002-2007 Xilinx , Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without Optimized for systems-As fast as ns pin-to-pin delays-As low as 13 A quiescent current Industry s best micron CMOS CPLD-Optimized architecture for effective logic synthesis. Refer to the CoolRunner -II family data sheet for architecture description. -Multi-voltage I/O operation to Available in multiple package options-100-pin VQFP with 80 user I/O-144-pin TQFP with 118 user I/O-132-ball CP ( ) BGA with 106 user I/O-208-pin PQFP with 173 user I/O-256-ball FT ( ) BGA with 184 user I/O-Pb-free available for all packages Advanced system features-Fastest in system programming ISP using IEEE 1532 (JTAG) JTAG Boundary Scan Test-Optional Schmitt-trigger input (per pin)-Unsurpassed low power management Dat
flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time. 0 XC2C256 CoolRunner-II CPLD DS094 (v3.2) March 8, 2007 00 Product Specification R
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