Transcription of ZCU104 Evaluation Board - Xilinx
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ZCU104 Evaluation Board - Xilinx
ZCU104 Evaluation BoardUser GuideUG1267 ( ) October 9, 2018 ZCU104 Board User Guide2UG1267 ( ) October 9, HistoryThe following table shows the revision history for this 2: Added Electrostatic Discharge 3: Updated introductory paragraphs in PS-Side: DDR4 Component Memory and PL-Side: DDR4 SODIMM Socket. In Table 3-12, updated GTR_REF_CLK_USB3 frequency to 26 MHz. In Table 3-24, replaced LVCMOS12 and LVCMOS18 with B: Updated appendix title and Overview. Removed ZCU104 Board Constraints File C: Updated D: Added Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925) to Xilinx FeedbackZCU104 Board User Guide3UG1267 ( ) October 9, of ContentsRevision History .. 2 Chapter 1: IntroductionOverview .. 5 Additional Resources .. 5 Block Diagram .. 6 Board Features .. 7 Board Specifications .. 9 Dimensions .. 9 Environmental .. 9 Operating Voltage .. 10 Chapter 2: Board Setup and ConfigurationBoard Component Location.
HP banks Six banks, total of 312 pins MIO banks Three banks, total of 78 pins PS-GTR transceivers (6 Gb/s) Four PS-GTR transceivers GTH transceivers (16.3 Gb/s) 20 GTH transceivers System logic cells 504K CLB flip-flops 461K Maximum distributed RAM 6.2 Mb Total block RAM 11 Mb UltraRAM 27 Mb DSP slices 1,728 Send Feedback
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