Transcription of Zynq UltraScale+ MPSoC Software Developer Guide
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Zynq UltraScale+ MPSoC Software Developer Guide
zynq ultrascale + MPSoCSoftware Developer GuideUG1137 ( ) July 1, 2020 Revision HistoryThe following table shows the revision history for this Summary07/01/2020 Version 10: Platform Management Unit FirmwareUpdated PMU Firmware Build Flags to add a new 12: ResetUpdated RPU Subsystem Restart for RPU only restartsupport E: XilSecure Library Additional H: XilFPGA Library Additional Version Embedded FlowUpdated SDK flows to Vitis Embedded Flow throughout Version 4: Software StackUpdated Multimedia Stack 7: System Boot and ConfigurationUpdated Miscellaneous FunctionsChapter 10: Platform Management Unit FirmwareAdded CSU/PMU Register Access and updated PMUF irmware Build FlagsChapter 11: Power Management FrameworkUpdated Sub-system Power ManagementAdded appendix01/18/2019 Version 2: Programming View of zynq ultrascale + MPSoCDevicesUpdated Boot Modes and System-Level Protections sectionsChapter 3: Development ToolsAdded Device Tree GeneratorChapter 4: Software StackRemoved XilRSA referencesChapter 8: Security FeaturesUpdated Configuring XMPU RegistersChapter 9: Platform ManagementUpdated Power Management FrameworkChapter 10: Platform Management Unit FirmwareUpdated PMU Firmware Build Flags, FPD WDT, and PMUF irmware Memory Layout and FootprintChapter 12: ResetUpdated Warm Restart with a note about on-chip memory(OCM)Chapter 16: Boot Image CreationRemoved content and updated the chapter with a shortdescript
11/15/2017 v5.0 • In Chapter1: ° Updated Prerequisites section. •In Chapter2: ° Updated Boot Process section. ° Updated Security section. •In Chapter4: ° Updated FreeRTOS Software Stack section. •In Chapter7: ° Added FSBL Build Process section. ° Added Setting FSBL Compilation Flags section. ° Updated Boot Modes section. •In Chapter8: ° Updated Boot Time Security section.
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