Example: confidence
And jitter using systemverilog assertions
Found 2 free book(s)
Pragmatic Simulation-Based Verification of Clock Domain ...
www.verilab.comCopyright © 2006 Verilab & DVCon - 1 - DVCon 2006 Pragmatic Simulation-Based Verification of Clock Domain Crossing Signals and Jitter using SystemVerilog Assertions
Assertion-Based Verification using SystemVerilog
www.verilab.comTitle: Microsoft PowerPoint - svug_2007 [Read-Only] Author: Katherine Garden Created Date: 10/15/2007 8:40:10 AM