always @(posedge clk ) begin - MIT OpenCourseWare
Digital Design Using Verilog ) begin mo d u l e b e t a (c l k, r e s e t, i r q, … I n p u t [3 1: 0] m e m _ d a t a; e n d m o d u l e I f (d o n e) $ f i n i s h; Figures by MIT OCW. P C + 4 + 4 * S X T ( C ) A E L 0 1 D a ta M e m o r y R D ... modules and interfaces Figure by MIT OCW. 6.884 – Spring 2005 02/04/05 L02 – Verilog 6 .
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