Verilog-2001 Quick Reference Guide - Sutherland HDL
• Comma separated sensitive lists (page 24) • Combinational logic sensitivity wild card (page 24) • Inferred nets with any continuous assignment (page 28) • Power operator (page 29) • Signed arithmetic extensions (page 7, 9, 11, 13, 29, 32, 38) • ANSI C style task/function I/O definitions (page 31, 32) • Re-entrant tasks (page 31)
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