Road to Chiplets: Architecture - events.meptec.org

1 Road to Chiplets: ArchitectureJuly 13 & 14, to ChipletsSandeep BharathiExecutive Vice President, SOC Central Engineering, Marvell MEPTEC, Microelectronics Packaging & Test Engineering CouncilJuly 13, 2021 2021 Marvell confidential. All rights not only monolithic? Different functions don t always want to be on the same chip: IO function, RF, analog and memory Due to: Technology fit Schedule Modularity Cost Reticle starting to get too small AMD EpycTM2 (Rome) processorsHBM memoryData converters 2021 Marvell confidential. All rights functions between multiple diesBreaking the problemto smaller piecesAddressing thefull reticle limitationOverall yieldimprovementDie Size: 750 mm2 Die Size: 300 mm2 Die Size: 50 mm2 2021 Marvell confidential. All rights SwitchMore silicon than whatfits in a Cost per mm2 vs. ChipletASIC Chip SizeRel.

2 Cost per mm2 Ratio vs. ChipletSmaller chipsBetter yieldLower cost 2021 Marvell confidential. All rights and interfacesChip-to-chip interface is required Chip partitioning increases the total silicon area 2021 Marvell confidential. All rights Area vs. cost considerationRelative cost per mm2 vs ChipletChip areaRel. cost per mm2 Large die yield poorly High cost per mm2750400 Smaller die yield significantly better Much lower cost per mm2 Can afford to add interface 2021 Marvell confidential. All rights cost considerations Increasing % of overall product cost 2 key variables for substrate cost: Size Typically determined by # of I/Os & power needed Build-up layers Adding a layer increases substrate cost by 25-30% Additional 2 layers (5-2-5 7-2-7) increases substrate cost by 55-70% Very large substrates are becoming increasingly expensive5060708090100110 CostSize (mm)OSAT #1 Substrate Pricing Trend6-2-67-2-78-2-8$$$$$$50607080901001 10 CostSize (mm)OSAT #2 Substrate Pricing Trend6-2-67-2-78-2-8$$$$$$ 2021 Marvell confidential.

3 All rights generation network switch 50T 50T network switch is around the corner Drives > 90mm package size Unless we find other ways to get the data off the Speed [Gbps]Aggregate chip bandwidth [Tb/s]Network switch bandwidth [Tbps]SERDES Speed [Gbps]Chip Bandwidth [Tbps] 2021 Marvell confidential. All rights on one chip?0100200300400500600700800 Chip edge limited size, Content area112G SerDes LanesChip edge limited chip sizeLR x4, 4 PLL AreaLR x4, 4 PLL, stacked AreaStacked LR SerDes cores (N&S)Drives 7-2-7 Single lane of LR SerDes coresEnables 5-2-535T50 TNot with 112G pam4 long reach SerDes Not enough Chip edge available Can only fit ~35T And only in 7-2-7 package 2021 Marvell confidential. All rights on one chip!Possible with 112G pam4 extra short reach Tight fit with x8 cores 5-2-5 package Easy fit with x16 cores 7-2-7 package0100200300400500600700800 Chip edge limited size, Content area112G SerDes LanesChip edge limited chip sizeXSR x8 Chip AreaXSR x16 Chip AreaLR x4, 4 PLL AreaLR x4, 4 PLL, stacked Areax8x1650T 2021 Marvell confidential.

4 All rights time to market advantage Technology scaling SerDes scaling benefits are relatively minimal in very advanced nodes 3nm silicon cost, yield and IP availability will be challenging N-1 node Interface IP available Create (N-1)nm interface chiplets N node Use XSR for ASIC-to-chiplet communication Leverage (N-1)nm interface chipletsContentSerDesTechnology scaling: Content vs. IP7nm5nm3nmLR off moduleXSR to ASIC5nmor3nm 2021 Marvell confidential. All rights for integrated optics Future of scalable systems High bandwidth die-to-die interconnect Chiplet based switching SerDes technology Low power / High bandwidth density Next generation optical interconnect Proven Optical and DSP technology Compact form-factor co-packaged optics (CPO) Enabling scalable, future proof electrical to optical systems Reduce power by moving the optics onto the package with the switchCPOSerDes chipletsASIC switch 2021 Marvell confidential.

5 All rights communication trends from copper to opticsSource: innovations will only be possible with silicon and optical integrationSiSilicon+OpOpticsHigher data rates and distance drive the move from copper to opticsData rateCopperOpticsTodayLong haul (1000km+)Metro (80km)Within building (2km)Within big floor (500m)Within small floor (100m)Within rack (3m)Within system (1m)Within card (<1m) 2021 Marvell confidential. All rights Carrier and Data Center switchingCPO JDAL iquid coolingIntegrated co-packaged opticsMulti-chip and Chiplet-based modular product portfoliosOn package copper cablesPassive and active 2021 Marvell confidential. All rights Chiplets and modular designs for multiple reasons Integrate content that doesn t want to be on the same chip Cost and yield Schedule and IP availability Chip-to-chip Interface determines what package technology is needed Package complexity must be optimized to reduce total product cost Co-optimization between Architecture and package is critical Chiplets and advanced packaging provide path to co-packaged opticsThank YouThank you sponsors!

6 Advantest receives highest ratings from customers in annual VLSI research Customer Satisfaction Survey for 2 consecutive years. Year-after-year the company has delivered on its promiseof technological excellence and it remains clear that Advantest keeps their customers successes central to their strategy. Congratulations on celebrating 33 years of recognitionfor outstanding customer satisfaction. Risto Puhakka, President VLSI researchGlobal customers name Advantest THE BEST supplier of test equipment in 2020 and 2021, with highest ratings in categories of:Technical Leadership Partnership Trust Recommended Supplier Field ServiceGlobal Companies Rate Advantest THE BEST ATE Company 2021 COPYRIGHT NOTICEThis presentation in this publication was presented at the Road to Chiplets: Architecture Workshop(July 13& 14, 2021).

7 The content reflects the opinion of the author(s) and their respective companies. The inclusion of presentations in this publication does not constitute an endorsement by MEPTEC or the is no copyright protection claimed by this publication. However, each presentation is the work of the authors and their respective companies and may contain copyrighted material. As such, it is strongly encouraged that any use reflect proper acknowledgement to the appropriate source. Any questions regarding the use of any materials presented should be directed to the author(s) or their