Successive Approximation ADCs - lumerink.com

1 Department of Electrical and Computer EngineeringVishal Saxena-1- Successive Approximation ADCsVishal SaxenaVishal Saxena-2- Successive Approximation ADCV ishal Saxena-3-0 Resolution[Bits]51015201k10k100k1M10M100 M1G10 GSample Rate [Hz]NyquistOversamplingIntegratingOversa mplingSuccessive ApproximationAlgorithmicSubrangingPipeli neFolding & InterpolatingFlashInterleaving1 level/Tclk1 word/OSR*Tclk1 bit/TclkPartial word/Tclk1 word/Tclk100 GData Converter ArchitecturesVishal Saxena-4- Successive Approximation ADC Binary search over DAC inputs N*Tclkto complete N bits Successive Approximation register or SAR High accuracy achievable (16+ bits) Relies on highly accurate comparator Moderate speeds (typically MHz parts) Saxena-5-Binary Search Algorithm DAC output gradually approaches the input voltage Comparator differential input gradually approaches Saxena-6-Binary Search Algorithm Saxena-7-High Performance ExampleVishal Saxena-8-Charge Redistribution SAR ADC 4-bit binary-weighted capacitor array DAC (akacharge scaling DAC) Capacitor array samples input when 1is asserted (bottom-plate) Comparator acts as a zero crossing detector Practical implementation is fully-differentialSARDo 1eVX2 CCC8C4 CVRVi 1 1 1 1 1 Vishal Saxena-9-Charge Redistribution (MSB)SARDo 1eVX2 CCC8C4 CVRVi 1 1 1 1 1 RiRiRX4X3210 XiV 8C - V 16 CVV 16C = V - V C - V C + C + C + CV- V16C2 Start with C4connected to VRand others to 0 ( SAR=1000)Vishal Saxena-10-Comparison (MSB)

2 If VX< 0, then Vi> VR/2, and MSB = 1, C4remains connected to VR If VX> 0, then Vi< VR/2, and MSB = 0, C4is switched to groundVXt01 MSBS ample1iRXV2V V:TEST MSB Vishal Saxena-11-Charge Redistribution (MSB 1) RiiRXXXRiV 12C V 16C3V 16 CVV12C V 4 CVVV16C4 SARDo 1eVX2 CCC8C4 CVRVi 1 1 1 1 1 SAR=1100 Vishal Saxena-12-Comparison (MSB 1) If VX< 0, then Vi> 3VR/4, and MSB-1 = 1, C3remains connected to VR If VX> 0, then Vi< 3VR/4, and MSB-1 = 0, C3is switched to ground XRi3 MSB -1 TEST : VVV4 VXt010 MSBS ample12 Vishal Saxena-13-Charge Redistribution (Other Bits)Test completes when all four bits are determined w/ four charge redistributions and comparisonsSARDo 1eVX2 CCC8C4 CVRVi 1 1 1 1 1 SAR=1010, and so Saxena-14-After Four Clock Usually, half Tclkis allocated for charge redistribution and half for comparison + digital logic VXalways converges to 0 (Vosif comparator has nonzero offset)VXt01001 MSBLSBS ample1234 Vishal Saxena-15-Summing-Node Parasitics If Vos= 0, CPhas no effect eventually.

3 Otherwise, CPattenuates VX Auto-zeroing can be applied to the comparator to reduce offsetSARDo 1e2 CCC8C4 CVRVi 1 1 1 1 1 CPVosVishal Saxena-16-SAR ADC Considerations Power efficiency only comparator consumes DC power Conversion rate typically limited by finite bandwidth of RC network during sampling and bit-tests For high resolution, the binary weighted capacitor array can become quite large 16-bit resolution, Ctotal~100pF for reasonable kT/C noise contribution If matching is an issue, an even larger value may be needed if matching dictates Cmin=10fF, then 216 Cmin=655pFVishal Saxena-17-SAR ADC Considerations contd. Comparator offset Vosintroduces an input-referred offset ~ (1+CP/ Cj)*Vos CPin general has little effect on the conversion (VX 0 at the end of the search) however, VXis always attenuated due to charge sharing of CP Binary search is sensitive to intermediate errors made during search if an intermediate decision is wrong, the digitization process cannot recover DAC must settle into LSB bound within the time allowed Comparator offset must be constant (no hysteresis or time-dependent offset) Non-binary search algorithm can be used (Kuttner, ISSCC 02)Vishal Saxena-18-SAR ADC Considerations contd.

4 Commonly used techniques Implement "two-stage" or "multi-stage" capacitor network to reduce array size [Yee, JSSC 8/79] Split DAC or C-2C network Calibrate capacitor array to obtain precision beyond raw technology matching [Lee, JSSC 12/84]Vishal Saxena-19-SAR ADC Speed Estimation Model RC network when VIN is charged Replace switches with R s Assume switches are sized proportional to capacitorsVishal Saxena-20-SAR ADC Speed Estimation contd. Speed limited by RC time constant of capacitor array and switches For better than LSB accuracy Sets minimum value for the charging time TVishal Saxena-21- Vishal Saxena and Venkatesh Acharya21 Fully-differential ImplementationVishal Saxena-22-Recap: Advantages of SAR ADC Mostly digital components good for technology scaling No linear, high precision amplification is required fast, low power Minimal hardware 1 comparator is neededVishal Saxena-23-SAR Evolution Digital friendly architecture in scaled CMOS has renewed interest in SAR innovationVishal Saxena-24-Limitations of Synchronous SAR Cost High-speed internal clock needed Speed Limitation Worst-case cycle time Margin for clock jitter Vishal Saxena-25-Asynchronous SAR Concept Self-timed Asynchronous comparisons Master clock used for synchronizing with the sample rateVishal Saxena-26-How much comparison time is saved?

5 Conv. time between sync. and async. SAR, assuming regenerative comparator is used. It varies with residue voltage profile Vishal Saxena-27-Asynchronous SAR ADC Concept Vishal Saxena-28-Asynchronous SAR ADC Concept Dynamic to save power and generate ready signal Reset switches for fast recovery Ready signal is generated by NAND gate! Vishal Saxena-29-Monotonic Capacitor Switching Monotonic switching procedure Input-common mode voltage gradually converges to ground Exploit differential configuration Asynchronous comparisons Switching energy reduced by 81%Vishal Saxena-30-Monotonic Capacitor Switching contd. Vishal Saxena-31-Monotonic Capacitor Switching contd. Conventional switching procedure Vishal Saxena-32-Monotonic Capacitor Switching contd. Monotonic switching procedureVishal Saxena-33-Monotonic Capacitor Switching contd.

6 Vishal Saxena-34-Loop-unrolled SAR ADC Use Ncomparators for each bit of conversion loop unrolling Asynchronous individual comparisons 6-bit Serial links applicationVishal Saxena-35-Loop-unrolled SAR ADC contd. High speed comparator IDAC for offset cancellation MetastabilitydetectionVishal Saxena-36-Time Interleaving Sampling rate scale proportionally to the number of interleaved channels Calibration is required for inter-channel mismatch Relaxed clock distribution For example: 8bit 56GS/s 320 of 175MS/s SAR (Fujitsu) Vishal Saxena-37-90GS/s 8bit with 64x Time Interleave Two comparators ping-pong in two consecutive conversions implemented in 32nm SOI Vishal van de Plassche, CMOS Integrated Analog-to-Digital and Digital-to-Analog Converters, 2ndEd., Springer, Chiu, Data Converters Lecture Slides, UT Dallas Boser, Analog-Digital Interface Circuits Lecture Slides, UC Berkeley 2011.