IEEE 802.3ba 40 and100 Gigabit Ethernet Architecture

1 ieee 40 and100 Gigabit Ethernet ArchitectureIlango Ganga, IntelIEEE task force Chief EditorIEEE ComSoc SCV Santa Clara,CA, Oct 20101 Outline ieee overview 40 and 100 Gb/s Ethernet layer diagram 40 and 100 Gb/s sublayers 40 and 100 Gb/s Architecture Compatibility interfaces 40 and 100 Gb/s implementation examples SummaryIEEE ComSoc SCV Santa Clara,CA, Oct 20102 ieee 40 and 100 GbEoverview Addresses the needs of computing, network aggregation and core networking applications Common Architecture for both 40 Gb/s and 100 Gb/s Ethernet Uses ieee Ethernet MAC and frame format The Architecture is flexible and scalable Leverages existing 10 Gb/s technology where possible Defines physical layer technologies for backplane, copper cable assembly and optical fiber medium ieee standard was ratified in Jun 2010 ieee ComSoc SCV Santa Clara,CA, Oct 20103 ieee 40G/100G summary Physical Layer SpecificationsPort TypeDescription40 GbE100 GbESolution Space40 GBASE-KR4Up to at least 1m backplane 4 x 10 Gb/s40 GBASE-CR4100 GBASE-CR10Up to at least 7m cu (twin-ax) cable 4 x 10 Gb/s 10 x 10 Gb/s40 GBASE-SR4100 GBASE-SR10Up to at least 100m OM3 MMF(150m OM4 MMF) 4 x 10 Gb/s 10 x 10 Gb/s40 GBASE-LR4Up to at least 10km SMF 4 x 10 Gb/s100 GBASE-LR4Up to at least 10km SMF 4 x 25 Gb/s100 GBASE-ER4Up to at least 40km SMF 4 x 25 Gb/s4 ieee ComSoc SCV Santa Clara,CA, Oct 201040 and 100 GbE layer modelIEEE ComSoc SCV Santa Clara,CA, Oct 20105 LLC (LOGICAL LINK CONTROL) OR OTHER MAC CLIENTMAC CONTROL (OPTIONAL)

2 MAC MEDIA ACCESS CONTROLRECONCILLIATIONHIGHER LAYERSMEDIUMMDIPCSPMAPMD40 GBASE-SR4/LR440G Fiber PHYsXLGMIIMEDIUMMDI40 GBASE-CR440G Copper cable assy PHYXLGMIIPCSFEC1 PMAPMDANMEDIUMMDI40 GBASE-KR440G Backplane PHYXLGMIIPHYSICALDATA LINKNETWORKTRANSPORTSESSIONPRESENTATIONA PPLICATIONNote: 1 . KR4, CR4 & CR10 may use optional FEC 2. XLGMII and CGMII are optional interfacesMEDIUMMDIPCSPMAPMD100 GBASE-SR10/LR4/ER4100G Fiber PHYsCGMIIMEDIUMMDI100 GBASE-CR10100G Copper cable assy PHYCGMIIPCSFEC1 PMAPMDANPCSFEC1 PMAPMDAN40 and 100 GbE sublayers MAC Same as ieee MAC specified in Clause 4 / Annex 4A Data Encapsulation, Ethernet framing, addressing, error detection ( CRC) RS (Reconciliation sublayer) The RS converts the MAC serial data stream to the parallel data paths of XLGMII (40 Gb/s) or CGMII (100 Gb/s) Provides alignment at the beginning frame, while maintaining total MAC transmit IPG 40 GBASE-R and 100 GBASE-R PCS (Physical Coding sublayer) Encodes 64 bit data & 8 bit control of XLGMII or CGMII to 66 bit code groups for communication with 40 GBASE-R and 100 GBASE-R PMA (64B/66B encoding)

3 Distributes data to multiple lanes, provides lane alignment and deskew Management interface to control and report status Forward Error Correction sublayer Optional sublayer for 40 GBASE-R and 100 GBASE-R to improve the BER performance of copper and backplane PHYs Uses the same FEC functions as defined in Clause 74 Operates on a per PCS lane basis at a rate of GBd for 40G and GBd for 100 GIEEE ComSoc SCV Santa Clara,CA, Oct 2010640 and 100 GbE sublayers ..2 40 GBASE-R and 100 GBASE-R PMA (Physical Medium Attachment) Adapts PCS to a range of PMDs Provides bit level multiplexing or mapping from n lane to m lanes Provides clock and data recovery Provides optional loopback and test pattern geneneration/checking functions 40 GBASE-R and 100 GBASE-R PMD (Physical Medium Dependent) Interfaces to various transmission medium ( , backplane, copper or optical fiber medium) Transmission/reception of data streams to/from the underlying medium Provides signal detect and fault function to detect fault conditions 40G PMDs: 40 GBASE-KR4, 40 GBASE-CR4, 40 GBASE-SR4, 40 GBASE-LR4 100G PMDs.

4 100 GBASE-CR10, 100 GBASE-SR10, 100 GBASE-LR4, 100 GBASE-ER4 Auto-Negotiation Clause 73 Auto-Negotiation is used for copper and backplane PHYs to detect the capabilities of the link partners and configure the link to appropriate mode Allows FEC capability negotiation, and provides parallel detection capability to detect legacy PHYs Management interface Uses the optional MDIO/MDC management data interface specified in Clause 45 for management of 40 and 100 Gigabit Physical layer devicesIEEE ComSoc SCV Santa Clara,CA, Oct 2010740 GbE Architecture XLGMII1(intra-chip) Logical, data/control, clock, no electrical specification 40 GBASE-R PCS 64B/66B encoding Lane distribution and alignment XLAUI1(chip-to-chip or chip-to-module)1 GBaud electrical interface 4 lanes Physical instantiation of PMA service interface FEC service interface Abstract PMA service interface Abstract, can be physically instantiated as XLAUI electrical interface XLPPI3(chip-to-module) GBaud electrical interface 4 lanes, optional for use with non retimed 40 GBASE-SR4/LR4 optical PHY modules PMD service interface LogicalIEEE ComSoc SCV Santa Clara,CA, Oct 20108 MEDIUMMDIFEC2 PMD40 GBASE-RFEC service interface (Abstract)PMA service interface (Abstract)PMD service interface XLPPI3, 4 lanes40 GBASE-R PCSXLGMII1 (Logical)RS, MAC AND HIGHER LAYERSPMA (4:4 mapping)PMA service interface XLAUI1, 4 lanesNote: 1.

5 Optional2. Optional for 40G Cu & backplane PHYs3. Optional for 40G optical PHYsPMA (4:4 mapping)AN2100 GbE Architecture CGMII1(intra-chip) Logical, data/control, clock, no electrical specification 100 GBASE-R PCS 64B/66B encoding Lane distribution and alignment CAUI1(chip-to-chip or chip-to-module) GBaud electrical interface 10 lanes Physical instantiation of PMA service interface FEC service interface Abstract PMA service interface Abstract, can be physically instantiated as CAUI electrical interface CPPI3(chip-to-module) GBaud electrical interface 10 lanes, for use with non retimed 100 GBASE-SR10 optical modules PMD service interface LogicalIEEE ComSoc SCV Santa Clara,CA, Oct 20109 Note: 1. Optional2. Optional for 100G Cu PHY3. Optional for 100 GBASE-SR10 PHY4. Conditional based on PHY typeMEDIUMMDIFEC2 PMD100 GBASE-RFEC service interface (Abstract)PMA service interface (Abstract)100 GBASE-R PCSCGMII1(logical)RS, MAC AND HIGHER LAYERSPMA (20:10 mapping)PMA4(10:4 mapping)PMA service interface (Abstract or CAUI1)PMD service interface (Abstract)PMA4(10:10 mapping)PMA service interface CAUI1, 10 lanesAN2100 GbE Architecture .

6 2 100 GbE Architecture diagram with CPPI CPPI3is physical instantiation of PMD service interface for 100 GBASE-SR10 PHYsIEEE ComSoc SCV Santa Clara,CA, Oct 201010 Note: 1. Optional2. Optional for 100G Cu PHY3. Optional for 100 GBASE-SR10 PHYMEDIUMMDIFEC2 PMD100 GBASE-RFEC service interface (Abstract)PMA service interface (Abstract)100 GBASE-R PCSCGMII1(logical)RS, MAC AND HIGHER LAYERSPMA (20:10 mapping)PMD service interface CPPI3, 4 lanesPMA(10:10 mapping)PMA service interface CAUI1, 10 lanesOptional compatibility interfaces XLGMII and CGMII (40 Gigabit and 100 Gigabit Media Independent Interface) Interface between MAC and PHY layers for intra-chip connectivity Logical definition, data width, control, clock frequency, no electrical or mechanical specifications Independent 64 bit transmit and receive data paths, 8 Tx and Rx control signals Clock is 1/64thof MAC data rate Provides a point of interoperability for multi vendor MAC and PHY implementations XLAUI and CAUI (40 Gigabit and 100 Gigabit attachment unit interface) Interface between MAC & PHY layers for chip-to-chip or chip-to-module connectivity Common electrical specification for XLAUI and CAUI GBaud per lane differential signaling 4 lanes in each direction for XLAUI (40 Gb/s) and 10 lanes in each direction for CAUI (100 Gb/s)

7 XLPPI and CPPI (40 Gigabit and 100 Gigabit parallel physical interface) Chip-to-module interface for use with non retimed optical modules for 40 GBASE-SR4, 40 GBASE-LR4 and 100 GBASE-SR10 PMDs XLPPI is physical instantiation of PMD service interace for 40 GBASE-SR4/LR4 PHYs CPPI is physical instantiation of PMD service interace for 100 GBASE-SR10 PHYs GBaud per lane differential signaling 4 lanes in each direction for XLPPI and 10 lanes in each direction for CPPIIEEE ComSoc SCV Santa Clara,CA, Oct 201011 Electrical interfaces Illustration of Inter-sublayer interface and Medium dependent interfaceIEEE ComSoc SCV Santa Clara,CA, Oct 20101240 GMACPCSPMD(x4)FECXLAUI40 GBASE-KR4/40 GBASE-CR4(w/ FEC chip)PMA(4:4)PMA(4:4)PMA(4:4)XLAUII nter-Sublayer interfaceMedium dependent interfaceBackplane or copper mediumChip to Chip or chip to module electrical specification XLAUI/CAUI and MDI have different electrical characteristicsPMA(4:4)PMD specification defines MDI electrical characteristics4 lanes 4 lanes 40 GbE implementation examplesIEEE ComSoc SCV Santa Clara,CA, Oct 20101340 GMACPCSPMD(x4)XLAUI40 GMACPCSPMD(x4)XLPPI40 GBASE-SR4 or LR4(4 lanes or 4 WDM lanes)PMA(4:4)40 GMACPCSPMD(x4)FEC40 GBASE-CR4 or KR4(w/ external PHY chip)PMA(4:4)PMA(4:4)PMA(4:4)XLAUIPMA(4: 4)XLPPIE xternal Transceiver/Re-timer Integrated with MAC Optical ModuleMAC integrated with XLPPIO ptical ModuleIntegrated with MAC External Cu / Backplane PHY40 GMACPCSPMD(x4)40 GBASE-CR4 or KR4(integrated PHY)PMA(4.)

8 4)Integrated MAC & PHYFECC opper or backplane mediumCopper or backplane mediumMultimode optical fiber mediumMultimode or single mode optical fiber mediumPMA(4:4)40 GBASE-SR4 or LR4(4 lanes or 4 WDM lanes)4 lanes 4 lanes 4 lanes 4 lanes 4 lanes 4 lanes 100 GbE implementation examplesIEEE ComSoc SCV Santa Clara,CA, Oct 201014100 GMACPCSPMD(x10)CAUI100 GBASE-SR10(10 lanes)100 GMACPCSPMA(10:4)CAUI100 GBASE-LR/ER4(4 WDM lanes)PMD(x4)PMA(20:10)PMA(20:10)100 GMACPCSPMD(x10)FEC100 GBASE-CR10(w/ external PHY w/FEC)PMA(20:10)PMA(20:10)PMA(10:20)CAUI PMA(10:10)CPPIE xternal Transceiver/Re-timer Optical ModuleIntegrated with MAC 100 GMACPCSPMD(x10)PMA(20:10)Integrated MAC & PHYFEC100 GBASE-CR10(integrated PHY)copper mediumcopper mediumMultimode optical fiber mediumSingle-mode optical fiber mediumExternal Cu / Backplane PHY10 lanes 10 lanes 10 lanes 10 lanes 10 lanes 10 lanes Summary 40 Gb/s and 100 Gb/s Ethernet use a common Architecture Addresses the needs of computing, network aggregation and core networking applications The Architecture is flexible and scalable to adapt tocurrent & future needs Leverages existing 10 Gb/s technology where possible ieee standard was ratified in Jun 2010 Future standards related to ieee Std ieee task force is developing a std for 40 Gb/s serial single mode fiber PMD 100 Gb/s backplane and copper cable assemblies Call For Interest scheduled for Nov 10 ieee ComSoc SCV Santa Clara,CA, Oct 201015