Working With Designs in Memory 6 - VLSI IP

1 Compiler User Guide6 Working with Designs in Memory6 design Compiler reads Designs into Memory from design files. Manydesigns can be in Memory at any time. After a design is read in, youcan change it in numerous ways, such as grouping or ungrouping itssubdesigns or changing subdesign chapter contains the following sections: Understanding design Terminology Reading Designs Listing Designs in Memory Setting the Current design Linking Designs Listing design Objects Specifying design Compiler User Guide Creating Designs Copying Designs Renaming Designs Changing the design Hierarchy Editing Designs Translating Designs From One Technology to Another Removing Designs From Memory Saving Designs Working with AttributesUnderstanding design TerminologyDifferent companies might use different terminology for Designs andtheir components.

2 This section describes the terminology used bythe Synopsys synthesis are circuit descriptions that perform logical are described in various design formats, such as VHDL,Verilog HDL, state machine, and Electronic Data Interchange Format(EDIF).Logic-level Designs are represented as sets of Boolean Designs , such as netlists, are represented asinterconnected Compiler User GuideDesigns can exist and be compiled independently of one another orcan be used as subdesigns in larger Designs . Designs are hierarchicalor DesignsA hierarchical design contains one or more Designs as subdesign can further contain subdesigns, creating multiplelevels of design hierarchy. Designs that contain subdesigns are calledparent 6-1 shows the three levels of hierarchy in the TOP 6-1 TOP design HierarchyTOP has three input ports and one output port.

3 The ports of CELL1and CELL2 are also pins of TOP. TOP and CELL1 are parent is instantiated twice in DesignsFlat Designs contain no subdesigns and have only one structural contain only library cells. TOPCELL1 CELL2 CELL2U1U1U2 Compiler User GuideDesign ObjectsA design consists of cells, nets, ports, and pins. It can containsubdesigns and references to subdesigns and library commands, attributes, and constraints are directed towarda design 6-2 shows the design objects in the TOP design 6-2 design Objects in TOP DesignCurrent DesignThe active design (the design being worked on) is called the currentdesign. Most commands are specific to the current design , that is,they operate within the context of the current , Instances, and ReferencesA unique instance of a design within another design is called ahierarchical cell.

4 A unique instance of a library cell within a design iscalled a leaf cell. The terminstance is also used to refer to a (also CELL1/port1)(also CELL1/port4)CELL1U1U2U1/pin3port3 Compiler User GuideSome commands work within the context of a hierarchical instanceof the current design . The current instance defines the active instancefor these instance-specific are defined by their attributes, such as their functions, wiring(connections), size, and design can contain multiple instances of identical subdesigns orlibrary cells. The instantiated subdesign or library cell is called thereference. Each instance points to the same reference but has aunique name to differentiate it from the other enable you to optimize every cell (such as a NAND gate)in a single design without affecting cells in other Designs .

5 The cellreferences in one design are independent of the same cell referencesin a different 6-3 shows the relationships among Designs , cells, 6-3 Cells and Cell ReferencesThe EXREF design contains two references: NAND2 andMULTIPLIER. NAND2 is instantiated three times, and MULTIPLIERis instantiated ReferencesNAND2 Compiler User GuideThe names given to the three instances of NAND2 are U1, U2, andU3. The references of NAND2 and MULTIPLIER in the EXREF designare independent of the same references in different information about resolving references, see Linking Designs onpage (networks) are the wires that connect ports to pins and pins toeach other. A net is the electrical connection between ports and pinsof a signal (from the first port or pin to the last in the signal).

6 PortsPorts are the inputs and outputs of a design . The signal flow of portsis defined as input, output, or are the input and output of cells within a design (such as gatesand flip-flops). The ports of a subdesign are pins within the Compiler User GuideReading DesignsTable 6-1 lists the design file formats supported by design Compiler supports input and output of all formats listed in thistable. All formats except .db, EDIF, equation, PLA, and state tablerequire special license 6-1 Supported design File internal database design Interchange Format (see theSynopsysEDIF 2 0 0 Interface User Guide) equation Logic Corporation (NDL) netlist NETED do Format (output only) Intermediate Format (input only) (Espresso) PLA state table design Language netlist Hardware Description Language (seetheHDL Compiler for Verilog ReferenceManual) Hardware Description Language (seetheVHDL Compiler Reference Manual) netlist format (see theFPGA CompilerUser Guide) Compiler User GuideDesign Compiler provides two ways to read design files.

7 Theread_file commanddc_shell>read_file -formatkeyword design_file Theanalyze andelaborate commandsdc_shell>analyze -formatkeyword design_filedc_shell>elaboratedesign_name Table 6-2 summarizes the differences between using theread_filecommand and using theanalyze andelaborate commands toread design design file exists in your host computer s file system. When youread a design file into design Compiler, it is stored in a Memory filein the Synopsys internal database (.db) format. The Memory file existsonly in the Working Memory of the design Compiler 6-2 read_file Versus analyze and elaborate CommandsComparisonread_file Commandanalyze and elaborate CommandsInput formatsAll formatsVHDL, VerilogWhen to useNetlists, precompiled Designs ,and so forthSynthesizing VHDL or VerilogDesignlibrariesCannot store analyzed resultsexcept in design library WORKCan store analyzed results inspecified design libraries (use theanalyze command option -library or -work)GenericsCannot pass parameters (mustuse directives in HDL)

8 Allows you to set parameter values onthe elaborate command lineArchitectureCannot specify architecture to beelaboratedAllows you to specify architecture tobe Compiler User GuideDesign Compiler names the Memory filepath_ Thepath_nameargument is the directory from which the original file wasread, and the design argument is the name of the design . If you laterread in a design that has the same Memory file name, DesignCompiler overwrites the original design . To prevent this, use the-single_file option with the read_file a Search PathYou can specify the design file location by using the complete pathor only the file name. If you specify only the file name, design Compileruses the search path defined in thesearch_pathvariable to locatethe design files.

9 design Compiler looks for the design files startingwith the leftmost directory specified in thesearch_path variableand uses the first library file it finds. When you specify the path, DesignCompiler does not use the search see where design Compiler finds a file when using the searchpath, use thewhich command. For example, enterdc_shell>which {/usr/designers/ }Reading .db FilesThe version of a .db file is the version of design Compiler that createdthe file. To read a .db file into design Compiler, the file must have thesame or earlier version than the version of design Compiler you Compiler User GuideIf you attempt to read in a .db file generated by a design Compilerversion later than the design Compiler version you are using, an errormessage appears.

10 The error message provides details about theversion HDL DesignsUse the following process to read HDL Designs :1. Analyze the top-level design and all subdesigns in bottom-uporder (to satisfy any dependencies).2. Elaborate the top-level design and any subdesigns that requireparameters to be assigned or DesignsTheanalyze command Reads an HDL source file Checks it for errors (without building generic logic for the design ) Creates HDL library objects in an HDL-independent intermediateformat Stores the intermediate files in a location you defineIf theanalyzecommand reports errors, fix them in the HDL sourcefile and runanalyze Compiler User GuideOnce a design is analyzed, you must reanalyze the design only whenyou change it. In addition, because design Compiler and theSynopsys VHDL System Simulator (VSS) use a common analyzer,you do not need to reanalyze VHDL files analyzed during simulation(unless they have changed).