Preparing for Optimization 7 - VLSI IP

1 Compiler User Guide7 Preparing for Optimization7 This chapter contains the following sections: Defining the Design Environment Selecting a Compile Strategy Setting Design Rule Constraints Setting Optimization Constraints Analyzing the Precompiled DesignPerform the tasks described in these sections before invoking theoptimization Compiler User GuideDefining the Design EnvironmentThe design environment is a set of attributes and constraints thatmodel the environment surrounding the design being design environment includes the following items: The operating conditions The wire load models The system interfaceFigure 7-1 illustrates the commands used to define thedesign 7-1 Commands Used to Define the Design Environmentset_wire_loadset_driveset_dri ving_cellset_fanout_loadset_loadset_oper ating_conditionsset_ Compiler User GuideDefining the Operating ConditionsIn most technologies, variations in operating temperature, supplyvoltage, and manufacturing process can strongly affect circuitperformance (speed).

2 These factors are called operating temperature variationIs unavoidable in the everyday operation of a design. Effects onperformance because of temperature fluctuations are most oftenhandled as a linear scaling effects, but some submicron siliconprocesses require nonlinear voltage variationConsiders deviations of the design s supply voltage from theestablished ideal value during day-to-day operation. Often acomplex calculation (using a shift in threshold voltages) isemployed, but a simple linear scaling factor is also used for logic-level performance variationAccounts for deviations in the semiconductor fabrication process variation is treated as a percentage variation inthe performance performing timing analysis, Design Compiler must consider theworst-case and best-case scenarios for the expected variations in theprocess, temperature, and voltage Compiler User GuideDetermining Available Operating Condition OptionsMost technology libraries have predefined sets of operatingconditions.

3 Use thereport_lib command to list the operatingconditions defined in a technology library. The library must be loadedin memory before you can run thereport_libcommand. To see alist of libraries loaded in memory, use thelist_libs example, to generate a report for the library my_lib, which is storedin , enter the following commands:dc_shell>read >report_lib my_libExample 7-1 shows the resulting operating conditions 7-1 Operating Conditions Report**Report : libraryLibrary: my_libVersion: : Mon Jan 4 10:56:49 1999**..Operating Conditions: Name Library Process Temp Volt Interconnect Model----------------------------------- ---------------------------------------- WCCOM my_lib worst_case_tree WCIND my_lib worst_case_tree WCMIL my_lib Operating ConditionsThere are no default operating conditions.

4 You must explicitly specifythe operating conditions for the current design by using theset_operating_conditions Compiler User GuideFor example, to set the operating conditions for the current design toworst-case commercial, enterdc_shell>set_operating_conditions WCCOM -lib my_libUse thereport_designcommand to see the operating conditionsdefined for the current Wire Load ModelsWire load modeling estimates the effect of wire length and fanout onresistance, capacitance, and area. These factors are used to estimatewire delays and are important for the overall speed of the wire load models define a fanout-to-length vendors develop the wire load models, based onstatistical information specific to the vendors process.

5 In the absenceof back-annotated wire delays, Design Compiler uses these wire loadmodels to estimate wire lengths in a design. See the Library Compilerdocumentation for more information about developing wire Compiler determines which wire load model to use for adesign, based on the following factors, listed in order of precedence:1. Explicit user specification2. Automatic selection based on design area3. Default specification in the technology Compiler User GuideIf none of this information exists, Design Compiler does not use awire load model. Without a wire load model, Design Compiler doesnot have complete information about the behavior of your targettechnology and cannot compute loading or propagation times for yournets; therefore, your timing information will be hierarchical designs, Design Compiler must also determine whichwire load model to use for nets that cross hierarchical Compiler determines the wire load model for cross-hierarchynets based on one of the following factors, listed in order ofprecedence:1.

6 Explicit user specification2. Default specification in the technology library3. Default mode in Design CompilerThe following sections discuss the selection of wire load models fornets and Hierarchical Wire Load ModelsDesign Compiler supports three modes for determining which wireload model to use for nets that cross hierarchical boundaries:topDesign Compiler models nets as if the design has no hierarchyand uses the wire load model specified for the top level of thedesign hierarchy for all nets in a design and its subdesigns. DesignCompiler ignores any wire load models set on subdesigns withtheset_wire_load top mode if you plan to flatten the design at a higher level ofhierarchy before Compiler User GuideenclosedDesign Compiler uses the wire load model of the smallest designthat fully encloses the net.

7 If the design enclosing the net has nowire load model, Design Compiler traverses the design hierarchyupward until it finds a wire load model. Enclosed mode is moreaccurate than top mode when cells in the same design are placedin a contiguous region during enclosed mode if the design has similar logical and Compiler determines the wire load model of each segmentof a net by the design encompassing the segment. Nets crossinghierarchical boundaries are divided into segments. For each netsegment, Design Compiler uses the wire load model of the designcontaining the segment. If the design containing a segment hasno wire load model, Design Compiler traverses the designhierarchy upward until it finds a wire load segmented mode if the wire load models in your technologyhave been characterized with net 7-2 shows a sample design with a cross-hierarchy net,cross_net.

8 The top level of the hierarchy (design TOP) has a wire loadmodel of 50x50. The next level of hierarchy (design MID) has a wireload model of 40x40. The leaf-level designs, A and B, have wire loadmodels of 20x20 and 30x30, Compiler User GuideFigure 7-2 Wire Load Mode ExampleIn top mode, Design Compiler estimates the wire length of netcross_net, using the 50x50 wire load model. Design Compiler ignoresthe wire load models on designs MID, A, and enclosed mode, Design Compiler estimates the wire length of netcross_net, using the 40x40 wire load model (the net cross_net iscompletely enclosed by design MID).In segmented mode, Design Compiler uses the 20x20 wire loadmodel for the net segment enclosed in design A, the 30x30 wire loadmodel for the net segment enclosed in design B, and the 40x40 wireload model for the segment enclosed in design = topmode = enclosedmode = segmented50X5040X4040X4020X2030X30 Compiler User GuideDetermining Available Wire Load ModelsMost technology libraries have predefined wire load models.

9 Use thereport_lib command to list the wire load models defined in atechnology library. The library must be loaded in memory before yourun thereport_lib command. To see a list of libraries loaded inmemory, use thelist_libs wire load report contains the following sections: Wire Loading Model sectionThis section lists the available wire load models. Wire Loading Model Mode sectionThis section identifies the default wire load mode. If a librarydefault does not exist, Design Compiler uses top mode. Wire Loading Model Selection sectionThe presence of this section indicates that the library supportsautomatic area-based wire load model generate a wire load report for the my_lib library, enterdc_shell>read >report_lib my_libExample 7-2 shows the resulting wire load models report.

10 The librarymy_lib contains three wire load models: 05x05, 10x10, and library does not specify a default wire load mode (so DesignCompiler uses top as the default wire load mode) and supportsautomatic area-based wire load model Compiler User GuideExample 7-2 Wire Load Models Report**Report : libraryLibrary: my_libVersion: : Mon Jan 4 10:56:49 1999**..Wire Loading Model:Name : 05x05 Location : my_libResistance : 0 Capacitance : 1 Area : 0 Slope : Length Points Average Cap Std Deviation------------------------------- ---------------------------------------- - 1 : 10x10 Location : my_libResistance : 0 Capacitance : 1 Area : 0 Slope : Length Points Average Cap Std Deviation------------------------------- ---------------------------------------- - 1 : 20x20 Location : my_libResistance.