Writing RTL Code for Virtex-4 DSP48 Blocks with XST 8

1 By Edgard GarciaXilinx Consultant/DesignerMulti Video xilinx Virtex -4 family introduceda new high-performance concept for fastand complex DSP algorithm implementa-tion. The XtremeDSP DesignConsiderations User Guide, available onthe xilinx website ( ), describes how youcan take advantage of the DSP48 architec-ture and includes several you have to develop a real DSPapplication, you can of course instantiateeach DSP48 block and assign their respec-tive attribute values to obtain the correctbehavior. But did you know you can alsoinfer most of the useful DSP48 configura-tions by Writing very simple RTL code?Developing DSP algorithms in VHDL(or Verilog) is a nice way to maintaindesigns over a long period of time, but thesynthesis results must meet your perform-ance requirements.

2 In this article, I willshow you how to write RTL code to takefull advantage of Virtex-4 DSP48 ArchitectureThe Virtex-4 DSP48 architecture is exten-sively described in the XtremeDSP UserGuide. Let s start, however, with anoverview of some very important aspects ofDSP48 Blocks : DSP48 Blocks have two18-bit inputsto feed the multiplier. If you want towork with unsigned data, 17 bits isthe maximum width of the multiplierinputs. Don t forget to expand theunsigned data/coefficients by concate-nating one or more 0 to the most sig-nificant bit (MSB). Similarly, if usingthe adder/subtracter, its inputs andoutput will have to be 48 bits or lessfor signed arithmetic and 47 bits orless for the examples described in this arti-cle, we will use signed data. You will haveto use the Another important parameter fordescribing DSP behavior for Virtex-4 DSP48 Blocks is that all DSP48 inter-nal registers have a synchronous reset(using asynchronous reset will preventthe synthesis tool from using theDSP48 internal registers).

3 The resetfunctionality has priority, regardless ofOpCode or other control inputs. It is important to note that the laststage of the adder/subtracter can bedriven dynamically to take a 48-bitinput (from the output stage feedbackor from the DSP48 C or Pcin input)and to add or subtract another 48- or36-bit input (originating for mostcommon cases from the multiplieroutput). Writing RTL Code for Virtex-4 DSP48 Blocks with XST Journal Fourth Quarter 2005 Writing RTL code for your DSP applications is easy and Examples1. commonly used function is ourfirst example, useful for FIR filters and other DSP functions. Hereis the source code:library IEEE;use ;use ; Signed arithmetic is usedentity MULT_ACC isPort ( CK : in std_logic;RST : in std_logic; Synchronous resetAin, Bin : in std_logic_vector(17 downto 0); A and B inputs of the multiplierS : out std_logic_vector(47 downto 0)); Accumulator output end MULT_ACC;architecture Behavioral of MULT_ACC issignal ACC : std_logic_vector(47 downto 0); Accumulator outputbeginprocess(CK) beginif CK event and CK = 1 thenif RST = 1 thenACC <= (others => 0 );elseACC <= ACC + (AIN * BIN);end if;end if;end process;S <= ACC;end Behavioral;This example will be synthesized into a single DSP48 block noother logic resource is necessary.

4 The performance is about 180-200 MHz, depending on placement and Fully pipelined you need more per-formance and less dependency on place and route tools, you canstill improve the performance of the Multiplier_accumulator. TheDSP48 Blocks have internal input registers (zero, one, or two stagesfor A and B inputs), as well as one selectable multiplier output reg-ister. The following RTL code uses one level of registers at the A andB inputs, as well as the multiplier output register:library IEEE;use ;use ; Signed arithmetic is usedentity MULT_ACC isPort ( CK : in std_logic;RST : in std_logic; Synchronous resetAin, Bin : in std_logic_vector(17 downto 0); A and B inputs of the multiplierS : out std_logic_vector(47 downto 0)); Accumulator output end MULT_ACC;architecture Behavioral of MULT_ACC issignal AinR, BinR : std_logic_vector(17 downto 0); Registered Ain and Binsignal MULTR : std_logic_vector(35 downto 0); Registered multiplier outputsignal ACC : std_logic_vector(47 downto 0); Accumulator outputbeginprocess(CK) beginif CK event and CK = 1 thenif RST = 1 thenAinR <= (others => 0 );BinR <= (others => 0 );MULTR <= (others => 0 );ACC <= (others => 0 );elseAinR <= Ain;BinR <= Bin.

5 MULTR <= AinR * BinR;ACC <= ACC + MULTR;end if;end if;end process;S <= ACC;end Behavioral;This example will be synthesized by using just a single DSPblock. You can take advantage of the internal registers to greatlyimprove performance to more than 400 MHz for the slowestVirtex-4 speed grade, independent of the implementation (placeand route) Fully pipelined canimprove the design further by using a loadable multiplier accumu-lator. For more details, please refer to the class material of the Xilinxcourse, DSP Implementation Techniques for xilinx FPGAs ( ).Let s modify the previous code for the load functionality:library IEEE;use ;use ; Signed arithmetic is usedentity MULT_ACC_LD isPort ( CK : in std_logic;RST : in std_logic; Synchronous resetAin, Bin : in std_logic_vector(17 downto 0); A and B inputs of the multiplierLOAD : in std_logic; Active high LOAD commandS : out std_logic_vector(47 downto 0)); Accumulator output end MULT_ACC_LD;architecture Behavioral of MULT_ACC_LD issignal AinR, BinR : std_logic_vector(17 downto 0); Registered Ain and Binsignal MULTR : std_logic_vector(35 downto 0); Registered multiplier outputsignal ACC : std_logic_vector(47 downto 0); Accumulator output 48 bit ZERO constant used for MULTR sign extension to 48 bitsconstant ZERO : std_logic_vector(47 downto 0) := (others => 0 ).

6 Beginprocess(CK) beginif CK event and CK = 1 thenif RST = 1 then AinR <= (others => 0 );BinR <= (others => 0 );MULTR <= (others => 0 );ACC <= (others => 0 );elseAinR <= Ain;BinR <= Bin;MULTR <= AinR * BinR;if LOAD = 1 thenACC <= ZERO + MULTR; OpCode = x05elseACC <= ACC + MULTR; OpCode = x25end if;end if;end if;end process;S <= ACC;end Behavioral;Fourth Quarter 2005 Xcell Journal004. is another useful ver-sion of the multiplier accumulator. It is useful for multiplications ofdata buses of more than 18 bits (see Figure 1-18 in the XtremeDSPUser Guide). Here is the RTL code:library IEEE;use ;use ; Signed arithmetic is usedentity MULT_ACC_ADD isPort ( CK : in std_logic;RST : in std_logic;SEL : in std_logic;A_in, B_in : in std_logic_vector(17 downto 0);C_in : in std_logic_vector(47 downto 0);S : out std_logic_vector(47 downto 0));end MULT_ACC_ADD;architecture Behavioral of MULT_ACC_ADD isconstant ZERO : std_logic_vector(47 downto 0) := (others => 0 );signal AR, BR : std_logic_vector(17 downto 0);signal MULT : std_logic_vector(35 downto 0);signal Pout : std_logic_vector(47 downto 0);beginprocess(CK) beginif CK event and CK = 1 then if RST = 1 then AR <= (others => 0 );BR <= (others => 0 );MULT <= (others => 0 );Pout <= (others => 0 );else AR <= A_in;BR <= B_in;MULT <= AR * BR;if SEL = 0 then Pout <= C_in + MULT.

7 Opcode = 0x35 for C input 0x15 for PCIN input if SEL = 0 then Pout <= ZERO + MULT; Opcode = 0x05 for ZERO constant as input (Note 1)else Pout <= Pout + MULT; Opcode = 0x25 (Notes 2, 3)end if;end if;end if;end process;S <= Pout;end Behavioral;Note that the synthesis results are not currently as optimized aswe could expect with XST Some combinatorial logic will beused to implement the multiplexer between C_in and Pout, whilethe same function was available inside the DSP48 block. The per-formance is still 220 MHz for the -10 speed grade, and 270+ MHzfor -12. However, Synplify Pro provides the ideal implementa-tion with the same RTL : Adding ZERO to Pout is equivalent to the previouslydescribed load function. Note 2 : You can also use the 17-bit right shift on Pout by chang-ing this line as follows (at this time, this feature is supported onlyby Synplicity Synplify Pro ):else Pout <= ZERO + Pout(47 downto 17) + MULT;Note 3 : If for any reason you do not want to use the output reg-ister of the multiplier, you can write: Pout <= Pout + (AR * BR);instead of declaring a combinatorial multiplier output.

8 The result-ing RTL code is also more Symmetric simple but useful example is amultiplier with symmetric rounding (see Table 1-9 in theXtremeDSP User Guide). Assuming that you want to round theresult of the multiplication Ain x Bin to 20 bits, the following RTLcode will be synthesized in just one DSP48 block and one slice:library IEEE;use ;use ;entity ROUNDING isPort ( CK : in std_logic;RST : in std_logic;Ain, Bin : in std_logic_vector(17 downto 0);P : out std_logic_vector(19 downto 0));end ROUNDING;architecture Behavioral of ROUNDING isconstant ZERO : std_logic_vector(47 downto 0) := (others => 0 );signal AR, BR : std_logic_vector(17 downto 0);signal MULTR : std_logic_vector(35 downto 0);signal Pout : std_logic_vector(47 downto 0);signal Carry_in, Carry_inR : std_logic;beginprocess(CK) beginif CK event and CK = 1 thenCarry_in <= not(Ain(17) xor Bin(17));Carry_inR <= Carry_in;if RST = 1 thenAR <= (others => 0 );BR <= (others => 0 );MULTR <= (others => 0 );Pout <= (others => 0 ).

9 ElseAR <= Ain;BR <= Bin;MULTR <= AR * BR; Note that the following 4 operands adder will be implemented as a 3 operand one : ZERO is a constant that allows easy sign extension for the VHDL syntaxPout <= ZERO + MULTR + x 7 FFF + Carry_inR;end if;end if;end process;P <= Pout(35 downto 16);end Behavioral;This example will also work at 400 MHz for the Virtex-4 -10speed grade device and 500 MHz for the -12 speed grade one LUT and its associated slice flip-flop is used, as the sec-ond flip-flop is pushed inside the DSP48 block for carry of these examples can be used in a wide range of can see that they are very efficiently synthesized, and all of thelogic is mapped into the DSP48 Blocks . The performance for eachof these DSP functions is independent of the place and route make it easier for synthesis tools to recognize the DSP48 struc-00 Xcell Journal Fourth Quarter 2005ture, it is important to write the code in a simple way, giving yourtools the best option to pack your desired functions into each DSP48block.

10 For this reason, each code has been written in a single process. The more simple and compact your RTL code, the more effi-cient the synthesis result. Of course, depending on your synthesistool, other alternatives can also give you excellent results, but theywill be more dependent on the synthesis tools. Higher Complexity DesignsWhat happens when you need more complex DSP functions? Youcan use a similar approach for many complex DSP algorithm imple-mentations by describing each block separately to ensure optimalsynthesis results. You will find many other examples, most of them directly relat-ed to those explained in their algorithmic and schematic form, inthe XtremeDSP User article is excerpted from the application note, Virtex-4 DSP48 Inference, which is available at application note includes additional examples, such as.