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UDA1334ATS Low power audio DAC with PLL - NXP
www.nxp.com8.1.1 AUDIO MODE Audio mode is enabled by setting pin PLL0 to LOW. De-emphasis can be activated via pin DEEM/CLKOUT according to Table 5. In audio mode, pin SYSCLK/PLL1 is used to set the sampling frequency range as given in Table 1. Table 1 Sampling frequency range in audio mode 8.1.2 VIDEO MODE In video mode, the master clock is a 27 MHz ...