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And Synthesis Techniques For Asynchronous Fifo Design
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Simulation and Synthesis Techniques for Asynchronous …
www.sunburst-design.comSNUG San Jose 2002 Simulation and Synthesis Techniques for Rev 1.2 Asynchronous FIFO Design 3 word, the receiver would clock once to output the data word from the FIFO, and clock a second time to capture the data word into the receiver. That would be needlessly inefficient. The FIFO is empty when the read and write pointers are both equal.
Simulation and Synthesis Techniques for Asynchronous …
www.sunburst-design.comSNUG San Jose 2002 Simulation and Synthesis Techniques for Asynchronous Rev 1.2 FIFO Design with Asynchronous Pointer Comparisons 4 Figure 3 - FIFO is going empty because the rptr trails the wptr by one quadrant If the write pointer is one quadrant ahead of the read pointer, this indicates a "possibly going empty" situation as shown in Figure 3.