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Tutorial Cadence Design Environment

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Spectre Circuit Simulator Reference

Spectre Circuit Simulator Reference

eece.cu.edu.eg

The Spectre circuit simulator is often run within the Cadence ® analog circuit design environment, under the Cadence® design framework II. To see how the Spectre circuit simulator is run under the analog circuit design environment, read the Cadence Analog Design Environment User Guide.

  Design, Environment, Cadence, Design environment

Lab 1: Schematic and Layout of a NAND gate

Lab 1: Schematic and Layout of a NAND gate

www.doe.carleton.ca

Get familiar with the Cadence Virtuoso environment. Draw a schematic of a simple NAND gate and simulate it. Draw layout of a NAND gate using cell library, then run a design rule check (DRC), extract, run a layout versus schematic (LVS) and simulate the extracted circuit. Compare the schematic and extracted simulations.

  Design, Environment, Cadence

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