第1章 はじめに - seaj.or.jp

1 Factory Integration 1 Factory Integration WG 1 FI Factory Integration WG STRJ WG FI 1 2 3 4 FICS 5 SEAJ 2010 STRJ SEAJ ITRS ITRS ITRS2011 Factory Integration ITRS SEAJ Waste Reduction SEAJ TAT NPW 2011 1-1 FI 1-2 1 ITRS 2 ITRS 3 ITRS Factory Integration 2 1-3 1 2 3 4 5 6) TAT 7) NPW 8) 9)

2 FI FO Factory Operation PE Process Equipment AMHS* FICS Factory Integration 3 2 SEAJ ITRS FI CIP FI-2-1 (ITRS 2011 ) Table FAC3 Factory Operations Technology RequirementsYear of Production201120122013201420152016201720 182019 DRAM Pitch (nm) (contacted) [Should be (from ORTC Table 1 - 1-yr pull-in).]

3 ] Diameter (mm)300300300450450450450450450 Factory Cycle Time (days/ mask layer) offor 25 wafer 12 wafer hot-lot(average top 1% of lots) Wait Time Waste (WTW) (days /maskWTW for 25 wafer for 12 wafer Equipment Output Waste(EOW)45%35%35%25%25%25%25%25%20%Bot tle neck equipmentUtilization92%93%93%94%94%94%94 %94%95%Availability94%95%95%96%96%96%96% 96%96%Average delivery time (minutes) NPW activities versus productionwafers activities (wafer move count ratio)<7%<6%<6%<5%<5%<5%<5%<5%<5%Bidirec tional equipment functional visualizationpartialyesyesyesyesyesyesye syesSingle Wafer Manufacturing SystemyesManufacturable solutions exist, and are being optimizedManufacturable solutions are knownInterim solutions are known Manufacturable solutions are NOT known [1] X-factor X-Factor [2] [3] Factory Integration 4 FI-2-2 Table FI-2-2 Explanation of Items for Factory Operations Requirements Wafer diameter 300mm 2014 450mm Factory cycle time per mask layer (days)25 wafer lot (25 ) ( ))

4 / Factory cycle time per mask layer (days)12 wafer lot (25 ) ( )/ 1 25 1 30 / 30 45 12 Super hot-lot (average top 1% of lots) factory cycle time per mask layer / ( 1%) 1 5 Wait Time Waste (days); 25 wafers in a carrier ( ) 25 WTW( ) ( )/N[day/mask layer] N ; TR (25 ) CT25 CTSHL [days/mask layer] CT25 [days/mask layer] CTSHL [days/mask layer] Wait Time Waste (days); 12 wafers in a carrier 12 12 X-factor [1] X-factor ( ) (RPT) 1 1 RPT X-factor Equipment output waste (%).

5 25 wefers in a carrier, high mix production (%) 25 1 1 EOW EOW TH25-TH0 /TH0 100[%] TH25 25 Factory Integration 5 EOW Factory EOW ( TH25-TH0 /TH0 /N 100[%] FI ITWG Factory EOW EOW 25 High mix operation FAB 10 FAB 50 (1-10 ) 1 50 5 ( ) 50% Bottle neck equipment utilization and availability [2] [3] Availability Utilization (%) SEMI E10 1 25 setup idle processing time Average delivery time (minutes) ( ))

6 MES Overall NPW activities versus production wafers activities Bidirectional equipment functional visualization SECS 2 Single wafer manufacturing system WIP 2009 2009 Factory Integration 6 3 EFEM*, 300mm 2009 FO TR FI-3-2 FI-3-1 Table FI-3-1 Production Equipment Technology Requirements # 2007/2008 Metrics 2009 Editon 1 Overall NPW activities vsersus production wafers activities (wafer move count ratio)

7 FO 2 % capital equipment reused from previous node 3 Wafer edge exclusion 4 Lithography Equipment Qualification Duration 5 Process equipment availability (A80) 6 Metrology equipment availability (A80) 7 Equipment-induced non-value added time as a % of total processing time (high mix) 8 Ability to run different recipes and parameters for each wafer 9 248nm scanner productivity (wafers outs per week per tool) 10 193nm scanner productivity (wafers outs per week per tool) 11 Maximum allowed electrostatic field on wafer and mask surfaces (V/cm) for ESD 2011 2009 NGF 450mm 1) Bidirectional Visualization 2) Waste Reduction 3) Productivity Requirements 4) Potential Solutions 5) Energy Saving and Factory Environment 2009 3)NGF Requirement 450mm 3)Productvty Requirement Factory Integration 7 3-1 3-1-1 ITRS/STRJ FI-3-2 (ITRS 2011 ) Table FI-3-2 Production Equipment Technology Requirements (refer to ITRS 2011) FI-3-3 (ITRS 2011 ) Table FI-3-3 Explanation of Items for Production Equipment Requirements (refer to ITRS 2011) Process equipment availability(A80) (A80) 100% % % ( )

8 7 x24 80% 80% SEMI E10 A80 Metrology availability(A80) (A80) 100% % % ( ) 7 x24 80% 80% SEMI E10 Maximum allowed electrostatic field on wafer and mask surfaces (V/m) ESD V/m SEMI E78 E43 EFM (SEMI E78: Electrostatic Compatibility Guide to Assess and Control Electrostatic Discharge (ESD) and Electrostatic Attraction (ESA) for Equipment. SEMI E43: Guide for Measuring Static Charge on Objects and Surfaces.) Year of Production 2011 2012 2013 2014 2015 2016 2017 2018 2019 2020 2021 DRAM Pitch (nm) (contacted) 40 36 32 28 25 20 Wafer Diameter (mm) 300 300300450450450450450 450 450 450 Process equipment availability (A80) >92% >94%>94%>95%>95%>95%>95%>95% >96% >96% >96%Metrology equipment availability (A80) >96% >97%>97%>98%>98%>98%>98%>98% >98% >98% >98%Maximum allowed electrostatic field on wafer and mask surfaces (V/m)

9 For ESD 4,400 3,8003,5003,1002,8002,5002,2002,000 1,800 1,500 1,300 Factory Integration 8 2009201020112012201320142015201620172018 201920202021 / FI-3-1 (ITRS 2011 ) Figure FI-3-1 Production Equipment Potential Solutions (refer to ITRS 2011) Factory Integration 9 3-2 ITRS Waste Reduction 2007 3-2-1 Waste Reduction 2009 ITRS FO WTW Wait Time Waiste EOW(Equipment Out Waiste) 2011 ITRS Waste Reduction Virtual