物理屋のための電子回路論第 13 回 最終回

1 13 ( ).. ( ). 2016 1 17 . A-D/D-A .. D-A/A-D .. A-D/D-A CCD . D .. ( ) ( ) .. A-D (ADC) D-A . (DAC) LSI .. - .. (a) . n 2n . VS 2n R ( . ) 1, , 2n i i + 1 . i VS /2n MOS . i VS /2n . 8 256 MOS .. (b) DA n 1 R . n + 2 2R n MOS . 2R R 2R . 2R OP . OP 2R . 13-1. Vs d1 d2 d n-1 dn 2n R 2n Vs 2 n- 1. Output qn Decoder Rf 2R 2R 2R 2R. q2 2 R2 A1 - q1 R R R 2R. 2R A2 A n-1 An +. 1. R1. 0. (a) (b). D-A (a) (b) . FET n H ON . p H OFF . An k 1(H) 0(L) An . 2R 2 R . An 1 An 2R An . Ak+1 Ak 1 Ak 2R. VS 2R VS /3R . 1/2 1/2 OP . n k+1. VS 1 VS. Jout ( 0 0 1 0 0 ) = = 2k 3R 2 6 2n R. n k 1. Jout 2 {di } (di = 0 or 1, i = 1, , n). OP ( ) . n 1 Rf X. Vout ({di }) = n VS 2k dk ( ). 3 2 2R. k=1. AD . $%&.. t . !"#.. PWM.. t .. (pulse width modulation, PWM) . PWM .. 13-2. PWM . DA . PWM .. H PWM . - .. (sample and hold circuit) ( . ) DA .. (successive approximation) .. sample 12 and ! "# $ . hold MSB. LSB AD . DA . (AD . ) .. OP .. DAC . OP ( ) . 0 1 DAC .. AD .. AD . ADC.

2 DAC .. A A 100dB . 13-3. 10 V 1V TTL Vth 10 .. + difference sample &hold S amplifier . G=2. 2bit 2bit - . flush ADC DAC. ( ) . 2bit data AD .. 1st stage 2nd stage n-th stage . digital output . Data adder . 2 ADC .. A ADC .. ON . AD OP . ( ) AD ( . ) .. ADC 1 ( 1 ) . ACD .. PAM . (pulse code modulation, PCM) PCM .. DAC . PCM .. PCM (differential PCM, DPCM) DPCM PCM.. {xi } . x i = axi 1 i = xi ax i . PCM ( ) .. 13-4.. (filter) . (digital signal processing, DSP) 1 .. DSP . (digital signal processor) .. ( ) .. x0 x1 x2 x3 .. {xi } = (x0 , x1 , ) {yi } = (y0 , y1 , ). yn xn . k xi k + 1 y0 y1 y2 y3 .. F . yn = F (xn k , xn k+1 , , xn ) ( ).. x a xn y n = ax n + z=x+y xn T y n = x n -1. y (a) (b) (c). (a) (b) . (c) ( ) . F . xn x n-1 x n-2 x n-3. T T T .. (block diagram) . 2 3 -4. -4x n-3 . 2x n 3x n-1. F . + +. 2 x n +3 x n-1 2 x n +3 x n - 1 - 4 x n - 3 . ( ) . 3 (a) . (b) . (c) . 13-5.. yn = 2xn + 3xn 1 4xn 3 ( ).. z . z . ( )z . ( ) z ( ) .. X . X. X(z) = xn z n , Y (z) = yn z n ( ).

3 N=0 n=0. z . k z k z . Y (z) = 2X(z) + 3z 1 X(z) 4z 3 X(z) = (2 + 3z 1 4z 3 )X(z) ( ). H(z) ( ) . hn 3 H(z) = 2 + 3z 1 4z 3 ( ). 2.. n t = 0 z .. F ( ) . k X. -4 F (xn k , xn k+1 , , xn ) = aj xn j ( ). j=0.. k X. H(z) = ai z j ( ). j=0.. z . X(z) Y(z) . + H 1( z ). 2 H1 (z) H2 (z) . X(z) + . H 2( z ) H1 W (z) . Y (z) = H1 (z)W (z) = H1 (z)(X(z) + H2 (z)Y (z)), H1 (z). Y (z) = X(z). 1 H1 (z)H2 (z).. H1 (z). H(z) = ( ). 1 H1 (z)H2 (z). 13-6. ( ) . ( ). ( ) = ( ). 1 ( ). ( ) .. ( ) . (infinite impulse response, IIR) . (finite impulse response, FIR) . ( ) FIR . (Low, High, Band) . ( LPF HPF BPF) (band elimination filter, BEF) .. FIR . xn x n-1 x n-2 x n - k +1 x n-k T T T. a0 a1 a2 a k-1 ak FIR . + + + + yn ( ) . FIR ( ) . ( ) FIR ( ) . z = ei . k X. H(ei ) = aj e ij ( ). j=0.. F (xn , xn 1 ) = (xn xn 1 )/2 ( ).. cos( /2). H (ei ) = e i /2 ( ). i sin( /2).. [0, / ] H+ H . FIR .. Fd = [(xn + xn 1 ) (xn 1 + xn 2 )]/2 = [xn xn 2 ]/2 ( ).. Hd = (1 e 2i )/2 = ie i sin ( ).

4 13-7. 1 1. | H +|. | H -| | H d|. 0 (a) . w (2/ T ). 1 0 1 w (1/ T ) 2 3.. 1. ( ). 1 arg( H - ). arg( H d ). 2/ . 0 /2 (b). 0. arg( H + ) -1 (a) . -1. 1/ . 0 1 2 3. w (1/ T ). 0 w (2/ T ) 1 . (a) (b). (b) . 1/2T . IIR . FIR . IIR . yn . lim yn = 0, ( ). n . 0 . xn x n-1 x n-2 x n - k +1 x n-k y n-1 y n-2 y n - m +1 y n-m T T T T T T. a0 a1 a2 a k-1 ak b1 b2 b m-1 bm + + + + + + + +. yn IIR . IIR FIR .. k X m X. yn = al xn l + bj yn j ( ). l=0 j=1. z . k X m X. Y (z) = X(z) al z l + Y (z) bj z j ( ). l=0 j=1.. k X. al z l Y (z) l=0. H(z) = = m ( ). X(z) X. 1 bj z j j=1. 13-8.. IIR FIR . ( ) . ( ) z z |z| > 1 .. FIR Ramez . Scilab ramez . (window function method) . LPF ( LPF . ) LPF c . (. i 1, | | c , G(e )= ( ). 0, c < | | N. N = s /2 = / ( ) [ N , N ] . 2 N = s .. i c X 1 c ni . X 1. G(e )= sinc n e = c sinc(n c )z n ( ). N n= n N n= . n . c c / N LPF n . sinc sinc(n c ) . G(iw). gn 1. (LPF). ( ) . w 0. n . 0 wc wN n sinc(n c / N ) ( ) . FIR LPF ( ) sinc.)

5 Sinc(x) x 1/x (a) . (a) (b) (c). (a)( ) LPF n = 20 / N . c / N = (b) = 7 L = 20 ( ) (c). (a) (b) . 13-9. sinc sin .. (window function) . (Kaiser) . p . I 1 (n/L)2.. 0. wn = |n| L, ( ). I0 ( ). 0 |n| > L.. I0 0 L . (b) ( ) (c) . (Butterworth) ( . ) . IIR . n LPF . N 1 . X k (2k + 1) . (s) = , sk = rc exp i + ( ). s sk 2 2n k=0. uH (t) . n 1. X. (t) = uH (t) wk exp(sk t) ( ). k=0. = 1 ( ) . n 1 n 1. X X wk hn = hHn wk ensk , H(z) = . ( ). 1 exp(sk )z 1. k=0 k=0. ( ) . (s sk ) 1 (1 exp(sk )z 1 ) 1 ( ). ( ) IIR (impulse invariant method) . z (bilinear z-transform) . 1 z 1. s ( ). 1 + z 1.. 4 . b0 + b1 z 1 + b2 z 2 + b3 z 3 + b4 z 4. H(z) = ( ). 1 a1 z 1 a2 z 2 a3 z 3 a4 z 4. 4 .. cos( t + 0 ) exp[i( t + 0 )] /2 . 13-10. 100. 1. | H (2 p if )|. | H (2 p if )|. 10-2. | H (2 p if )|. 10-4. 1. 10-6. 0 200 400. 0 10-8 f (Hz). 1000 2000 3000 4000 5000 1000 2000 3000 4000 5000. (a) f (Hz) (b) f (Hz) (c). coef. 0 1 2 3 4. an 10 1. bn 10 3 10 2 10 2 10 2 10 3. z IIR-LPF.

6 (a) (b) 0 (c) . ( ) 10kHz, 1kHz z . sin i . (a) /2 . - (b) .. arg H ( iw ). p/2. + wN. H(iw) -w N w i % &' -p/2. (a) (b). (a) (b) . 2 . (phase-locked loop, PLL) . PLL . IC .. (a) PLL PLL . (voltage controlled oscillator, VCO) VCO ( . 0 PLL VCO . VCO . 0 VCO ( . ) .. 13-11. 23 !" !" ! "4 g2. +. 9: #$ . z -1. +, -. g1. 5678 /01 +. (a) (c). + mod mod + [ -p , p ] + + z -1. [ -p , p ]. - z -1 w 0t (b) (d). (a) (b) (c) (d).. (r). (a) (xn , xn (i)) . (i). xn n = arctan (r). ( ). xn VCO n (b) n n [ , ] 2 .. (c) IIR . g2. H(z) = g1 + ( ). 1 z 1. 2 (1 z 1 ) 1 1 z .. PLL .. VCO v . i v = i ( ) .. g2 < 2g1 + 4 ( ).. VCO. (d) VCO .. PLL . VCO FM . - A-D . - AD ( ) AD .. 2 (a) . 1 . 13-12. H . (b) H L PWM .. +. + !"#. - $%&'. (a) (b). (a) - (b) ) - .. (adaptive filter) (a).. FIR ( ) ai . IIR . FIR . (a) .. (b) (adaptive line enhancer) .. 2" 2". # $ %& #$%&. !" !" 78 9 : . - - # $ +, + #$+, +. + +. (a) (b). 3456. (a) (b) (a) . 13-13. HDL. (hardware description language, HDL).

7 LSI . PLD FPGA( ) .. HDL ( ) . HDL . very high speed IC VHDL . Verilog HDL .. HDL . HDL NAND .. -- Library declaration -------------- library IEEE;. use IEEE, ;. -- Entity declaration --------------- entity NAND_CIRCUIT is port(. A : in std_logic;. B : in std_logic;. C : out std_logc A ab );. C. B. end NAND_CIRCUIT;. -- Architecture declaration ---------- architecture RTL of NAND_CIRCUIT is signal ab : std_logic;. begin ab <= A and B;. C <= not ab;. end RTL;. 13-14.. use .. NAND generic . port .. = begin - end .. PLD FPGA. HDL programmable logic device (PLD) field programmable gate array (FPGA) IC (FPGA PLD ) IC .. (a) PLD NOT AND.. FPGA (b) . ON/OFF FF . (mixed signal FPGA). CPU .. TTL . CMOS PROM EPROM . EEPROM .. (a). (b). (a) PLD (b) FPGA . 13-15.. [1] A. V. Oppenheim, R. W. Shafer, Dicrete-Time Signal Processing (Prentice Hall, 1999). [2] M. H. Hayes, Statistical Digital Signal Processing and Modeling (Wiley and Sons, 1996). [3] S. C. Douglas, Introduction to Adaptive Filters in Digital Signal Processing Handbook Eds.

8 V. K. Madisetti and D. B. Williams (CRC Press, 1999). [4] PLL (CQ 2011). K A-D/D-A . A-D/D-A . DAC . / .. 24 DA IC AD 32 . - AD .. ADC/DAC .. ( ) .. AD7949 MUX. 8 ( ) .. (LPF) 14bit SAR ADC . IC 14 (successive approximation resistor) ADC . specification table .. 13-16. AD7949 specification table . A-D . A-D .. 13-17.