2.7 V To 5.5 V, 1-Channel, 8-Bit Parallel ADC (Rev. A)

1 V TO V, 1- channel , 8-Bit , Parallel ANALOG-TO-DIGITAL CONVERTER SLAS239A SEPTEMBER 1999 REVISED FEBRUARY 20001 POST OFFICE BOX 655303 DALLAS, TEXAS 75265featuresDFast Throughput Rate: MSPS at 5 V, 625 KSPS at 3 VDWide Analog Input: 0 V to AVDDDD ifferential Nonlinearity Error: < LSBDI ntegral Nonlinearity Error: < LSBDS ingle to Supply OperationDLow Power: 12 mW at 3 V and 35 mW at 5 VDAuto Power Down of 1 mA MaxDSoftware Power Down: 10 A MaxDInternal OSCDH ardware ConfigurableDDSP and Microcontroller CompatibleParallel InterfaceDBinary/Twos Complement OutputDHardware Controlled Extended SamplingDHardware or Software Start of ConversionapplicationsDMass Storage and HDDDA utomotiveDDigital ServosDProcess ControlDGeneral-Purpose DSPDI mage Sensor Processing descriptionThe TLV571 is an 8-Bit data acquisition systemthat combines a high-speed 8-Bit ADC and aparallel interface. The device contains two on-chip control registers allowing control of software conversion startand power down via the bidirectional Parallel port.

2 The control registers can be set to a default mode using adummy RD while WR is tied low allowing the registers to be hardware TLV571 operates from a single to power supply. It accepts an analog input range from 0 V toAVDD and digitizes the input at a maximum MSPS throughput rate at 5 V. The power dissipations are only12 mW with a 3-V supply or 35 mW with a 5-V supply. The device features an auto power-down mode thatautomatically powers down to 1 mA 50 ns after conversion is performed. In software power-down mode, theADC is further powered down to only 10 high throughput rate, simple Parallel interface, and low power consumption make the TLV571 an idealchoice for high-speed digital signal OPTIONSPACKAGETA24 TSSOP(PW)24 SOIC(DW) 40 C to 85 CTLV571 IPWTLV571 IDWC opyright 2000, Texas Instruments IncorporatedPRODUCTION DATA information is current as of publication conform to specifications per the terms of Texas Instrumentsstandard warranty.

3 Production processing does not necessarily includetesting of all be aware that an important notice concerning availability, standard warranty, and use in critical applications ofTexas Instruments semiconductor products and disclaimers thereto appears at the end of this data No internal connection1234 56789101112242322212019181716151413 CSWRRDCLKDGNDDVDDINT/EOCDGNDDGNDD0D1D2 NCAINAVDDAGNDREFMREFPCSTARTA1/D7A0/D6D5D 4D3DW OR PW PACKAGE(TOP VIEW) V TO V, 1- channel , 8-Bit , Parallel ANALOG-TO-DIGITAL CONVERTER SLAS239A SEPTEMBER 1999 REVISED FEBRUARY 20002 POST OFFICE BOX 655303 DALLAS, TEXAS 75265functional block diagramInternalClockCLKCSRDINT/EOCMUX8-B ITSAR ADCI nput Registersand Control LogicWRCSTARTREFPT hreeStateLatchAVDDD0 D5D6/A0D7/A1 REFMDVDDDGNDAGNDAINT erminal groundAIN23 IADC analog inputAVDD22 Analog supply voltage, V to VA0/D616I/OBidirectional 3-state data bus. D6/A0 along with D7/A1 is used as address lines to access CR0 and CR1 3-state data bus.

4 D7/A1 along with D6/A0 is used as address lines to access CR0 and CR1 clock inputCS1 IChip select. A logic low on CS enables the sample and conversion start input. The falling edge of CSTART starts sampling and the rising edgeof CSTART starts , 8, 9 Digital groundDVDD6 Digital supply voltage, V to VD0 D510 15I/OBidirectional 3-state data busINT/EOC7 OEnd-of-conversion/interruptNC24 Not connectedRD3 IRead data. A falling edge on RD enables a read operation on the data bus when CS is reference voltage (nominally ground). REFM must be supplied or REFM pin must be reference voltage (nominally AVDD). The maximum input voltage range is determined by the differencebetween the voltage applied to REFP and data. A rising edge on the WR latches in configuration data when CS is low. When using softwareconversion start, a rising edge on WR also initiates an internal sampling start pulse. When WR is tied to ground,the ADC in nonprogrammable (hardware configuration mode).

5 V TO V, 1- channel , 8-Bit , Parallel ANALOG-TO-DIGITAL CONVERTER SLAS239A SEPTEMBER 1999 REVISED FEBRUARY 20003 POST OFFICE BOX 655303 DALLAS, TEXAS 75265detailed descriptionanalog-to-digital SAR converter_+ChargeRedistributionDACSARR egisterREFMADC CodeControlLogicAinFigure 1 The TLV571 is a successive-approximation ADC utilizing a charge redistribution DAC. Figure 1 shows asimplified version of the sampling capacitor acquires the signal on Ain during the sampling period. When the conversion processstarts, the SAR control logic and charge redistribution DAC are used to add and subtract fixed amounts of chargefrom the sampling capacitor to bring the comparator into a balanced condition. When the comparator isbalanced, the conversion is complete and the ADC output code is frequency, fsThe TLV571 requires 16 CLKs for each conversion, therefore the equivalent maximum sampling frequencyachievable with a given CLK frequency is:fs(max) = (1/16) fCLKThe TLV571 is software configurable.

6 The first two MSB bits, D(7,6) are used to address which register to remaining six bits are used as control data bits. There are two control registers, CR0 and CR1, that are userconfigurable. All of the register bits are written to the control register during write cycles. A description of thecontrol registers is shown in Figure V TO V, 1- channel , 8-Bit , Parallel ANALOG-TO-DIGITAL CONVERTER SLAS239A SEPTEMBER 1999 REVISED FEBRUARY 20004 POST OFFICE BOX 655303 DALLAS, TEXAS 75265detailed description (continued)control registers0:Binary1: 2 sComplement0:ReservedBit,AlwaysWrite 00:INT. :INT. Register Zero (CR0)D4D5D3D2D1D0 PROGEOCCLKSELSWPWDNDon t Care0:HARDWARESTART(CSTART)A(1:0)=001:SO FTWARESTART0:INT1:EOC0:InternalClock1:Ex ternalClock0:NORMAL1:PowerdownReservedCo ntrol Register One (CR1)D4D5D1D0 OSCSPD0 Reserved0 ReservedOUTCODER eserved0:ReservedBitAlwaysWrite 0A(1:0)=010:ReservedBitAlwaysWrite 0D3D2 Don t CareDon t CareDon t Care0:ReservedBit,AlwaysWrite 0 Figure 2.

7 Input Data Formathardware configuration optionThe TLV571 can configure itself. This option is enabled when the WR pin is tied to ground and a dummy RDsignal is applied. The ADC is now fully configured. Zeros or default values are applied to both control ADC is configured ideally for 3-V operation, which means the internal OSC is set at 10 MHz and hardwarestart of conversion using conversion modesThe TLV571 provides two start of conversion modes. Table 1 explains these modes in more V TO V, 1- channel , 8-Bit , Parallel ANALOG-TO-DIGITAL CONVERTER SLAS239A SEPTEMBER 1999 REVISED FEBRUARY 20005 POST OFFICE BOX 655303 DALLAS, TEXAS 75265detailed description (continued)Table 1. Conversion ModesSTART OFCONVERSIONOPERATIONCOMMENTS FOR INPUTH ardware start(CSTART) = 0 Repeated conversions from AIN CSTART falling edge to start sampling CSTART rising edge to start conversion If in INT mode, one INT pulse generated after each conversion If in EOC mode, EOC will go high to low at start of conversion, and return highat end of rising edge must be applieda minimum of 5 ns before or after CLKrising = 1 Repeated conversions from AIN WR rising edge to start sampling initially.

8 Thereafter, sampling occurs at therising edge of RD. Conversion begins after 6 clocks after sampling has begun. Thereafter, if in INTmode, one INT pulse generated after each conversion If in EOC mode, EOC will go high to low at start of conversion and return high atend of external clock, WR and RD risingedge must be a minimum 5 ns beforeor after CLK rising the deviceThe device can be configured by writing to control registers CR0 and 2. TLV571 Programming ExamplesREGISTERINDEXD5D4D3D2D1D0 COMMENTREGISTERD7D6D5D4D3D2D1D0 COMMENTEXAMPLE1CR000000000 Normal, INT OSCCR101000000 BinaryEXAMPLE2CR000011100 Power down, EXT OSCCR1010000102 s complement outputpower downThe TLV571 offers two power down modes, auto power down and software power down. This device willautomatically proceed to auto power down mode if RD is not present one clock after conversion. Software powerdown is controlled directly by the user by pulling CS to 3.

9 Power Down ModesPARAMETERS/MODESAUTO POWER DOWNSOFTWARE POWER DOWN(CS = DVDD)Maximum power down dissipation current1 mA10 AComparatorPower downPower downClock bufferPower downPower downControl registersSavedSavedMinimum power down time1 CLK2 CLKM inimum resume time1 CLK2 V TO V, 1- channel , 8-Bit , Parallel ANALOG-TO-DIGITAL CONVERTER SLAS239A SEPTEMBER 1999 REVISED FEBRUARY 20006 POST OFFICE BOX 655303 DALLAS, TEXAS 75265detailed description (continued)reference voltage inputThe TLV571 has two reference input pins: REFP and REFM. The voltage levels applied to these pins establishthe upper and lower limits of the analog inputs to produce a full-scale and zero-scale reading respectively. Thevalues of REFP, REFM, and the analog input should not exceed the positive supply or be less than GNDconsistent with the specified absolute maximum ratings. The digital output is at full scale when the input signalis equal to or higher than REFP and is at zero when the input signal is equal to or lower than sampling, conversion, and data output in the device are started by a trigger.

10 This could be the RD, WR, orCSTART signal depending on the mode of conversion and configuration. The rising edge of RD, WR, andCSTART signal are extremely important, since they are used to start the conversion. These edges need to stayclose to the rising edge of the external clock (if it is used as CLK). The minimum setup and hold time with respectto the rising edge of the external clock should be 5 ns minimum. When the internal clock is used, this is not anissue since these two edges will start the internal clock automatically. Therefore, the setup time is always controlled sampling lasts 6 clock cycles. This is done via the CLK input or the internal oscillator ifenabled. The input clock frequency can be 1 MHz to 20 MHz, translating into a sampling time from s s. The internal oscillator frequency is 9 MHz minimum (ocillator frequency is between 9 MHz to 22 MHz),translating into a sampling time from s to s.