200b: x32 Mobile LPDDR4 SDRAM - files.pine64.org

1 Mobile LPDDR4 SDRAMMT53B256M32D1, MT53B512M32D2, MT53B1024M32D4 Features Ultra-low-voltage core and I/O power supplies VDD1 = ; nominal VDD2/VDDQ = ; nominal Frequency range 1600 10 MHz (data rate range: 3200 20 Mb/s/pin) 16n prefetch DDR architecture 2-channel partitioned architecture for low RD/WRenergy and low average latency 8 internal banks per channel for concurrent opera-tion Single-data-rate CMD/ADR entry Bidirectional/differential data strobe per byte lane Programmable READ and WRITE latencies (RL/WL) Programmable and on-the-fly burst lengths (BL =16, 32) Directed per-bank refresh for concurrent bank op-eration and ease of command scheduling Up to GB/s per die (2 channels x GB/s) On-chip temperature sensor to control self refreshrate Partial-array self refresh (PASR) Selectable output drive strength (DS) Clock-stop capability RoHS-compliant, green packaging Programmable VSSQ (ODT) terminationOptionsMarking VDD1/VDD2.

2 Array configuration 256 Meg x 32 (2 channels x16 I/O)256M32 512 Meg x 32 (2 channels x16 I/O)512M32 1024 Meg x 32 (2 channels x8 I/O x 2)1024M32 Device configuration 256M16 x 2 channel x 1 dieD1 256M16 x 2 channel x 2 dieD2 512M8 x 2 channel x 4 dieD4 FBGA green package 200-ball WFBGA (10mm x )NP 200-ball VFBGA (10mm x )NQ Speed grade, cycle time-062 625ps @ RL = 28/32 (x16 device) 625ps @ RL = 32/36 (x8 device) Operating temperature range 30 C to +85 CWT Revision:CTable 1: Key Timing ParametersSpeedGradeArrayconfigura-tionD eviceTypeClock Rate(MHz)Data Rate(Mb/s/pin)WRITE LatencyREAD LatencySet ASet BDBID isabledDBIE nabled-062256Mb x 32512Mb x 32x16 device16003200142628321024Mb x 32x8 device1600320014263236 Micron Confidential and ProprietaryPreliminary 200b: x32 Mobile LPDDR4 SDRAMF eaturesPDF: Rev.

3 B 4/16 EN1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are for evaluation and reference purposes only and are subject to change byMicron without notice. Products are only warranted by Micron to meet Micron s production data sheet AddressingThe table below shows the addressing for the 8Gb die density . Where applicable, a distinction is made betweenper-channel and per-die parameters. All bank, row, and column addresses are shown 2: Device AddressingConfiguration256M32 (8Gb)512M32 (16Gb)1024M32 (32Gb) 3 Die per package124 Device density (per die)8Gb8Gb8 GbDevice density (per channel)4Gb8Gb16 GbConfiguration32Mb x 16 DQ x 8 banksx 2 channels x 1 rank32Mb x 16 DQ x 8 banksx 2 channels x 2 ranks64Mb x 8 DQ x 8 banksx 2 channels x 2 ranks x 2 Number of channels (per die)222 Number of ranks per channel122 Number of banks (per channel)888 Array prefetch (bits) (per channel)256256128 Number of rows (per bank)32,76832,76865,536 Number of columns (fetch boundaries)646432 Page size (bytes)204820481024 Channel density (bits per channel)4,294,967,2968,589,934,59217,179 ,869,184 Total density (bits per die)8,589,934,5928,589,934,5928,589,934, 592 Bank addressBA[2:0]BA[2:0]BA[2:0]x16 Row addressesR[14:0]R[14:0] Column addressesC[9:0]C[9.]

4 0] x8 Row addresses R[15:0]Column addresses C[9:0]Burst starting address boundary64-bit64-bit64-bitNotes:1. The lower two column addresses (C0 C1) are assumed to be zero and are not transmitted on the CA Row and column address values on the CA bus that are not used for a particular density are "Don't Care."3. Refer to Byte Mode section for further information about 1024M32 (32Gb) Confidential and ProprietaryPreliminary200b: x32 Mobile LPDDR4 SDRAMSDRAM AddressingPDF: Rev. B 4/16 EN2 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights Number Ordering InformationFigure 1: Part Number ChartMT53B 256M32 D1NP-062WT:CMicron TechnologyProduct Family53 = Mobile LPDDR4 SDRAMO perating VoltageB = = 256 Meg x 32512M32 = 512 Meg x 321024M32 = 1024 Meg x 32 AddressingD1 = LPDDR4 , 1 dieD2 = LPDDR4 , 2 dieD4 = LPDDR4 , 4 dieDesign Revision:C = Third generationOperating TemperatureWT = 30 C to +85 CCycle Time 062 = 625ps, tCK RL = 32/36 (x8 device)tCK RL = 28/32 (x16 device)Package CodesNP = 200-ball WFBGA (Height max) NQ = 200-ball VFBGA (Height max) FBGA Part Marking DecoderDue to space limitations, FBGA-packaged components have an abbreviated part marking that is different from thepart number.

5 Micron s FBGA part marking decoder is available at timing diagrams, CMD is used as an indicator only. Actual signals occur on CA[5:0].VREF indicates VREFCA and Confidential and ProprietaryPreliminary200b: x32 Mobile LPDDR4 SDRAMPart Number Ordering InformationPDF: Rev. B 4/16 EN3 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights Description .. 17 General Notes .. 17 Package Block Diagrams .. 18 Ball Assignments and Descriptions .. 21 Package Dimensions .. 23MR0, MR[6:3], MR8, MR13 Readout .. 25 IDD Parameters .. 26 Functional Description .. 28 Monolithic Device Addressing .. 28 Simplified Bus Interface State Diagram .. 32 Power-Up and Initialization .. 33 Voltage Ramp .. 34 Reset Initialization with Stable Power .. 36 Power-Off Sequence.

6 37 Controlled Power-Off .. 37 Uncontrolled Power-Off .. 37 Mode Registers .. 38 Mode Register Assignments and Definitions .. 38 Commands and Timing .. 64 Truth Tables .. 64 ACTIVATE Command .. 67 Read and Write Access Modes .. 68 Preamble and Postamble .. 69 Burst READ Operation .. 72 Read Timing .. 74tLZ(DQS), tLZ(DQ), tHZ(DQS), tHZ(DQ) Calculation .. 74tLZ(DQS) and tHZ(DQS) Calculation for ATE (Automatic Test Equipment) .. 75tLZ(DQ) and tHZ(DQ) Calculation for ATE (Automatic Test Equipment) .. 76 Burst WRITE Operation .. 78 Write Timing .. 80tWPRE Calculation for ATE (Automatic Test Equipment) .. 81tWPST Calculation for ATE (Automatic Test Equipment) .. 81 MASK WRITE Operation .. 82 Mask Write Timing Constraints for BL16 .. 84 Data Mask and Data Bus Inversion (DBI[DC]) Function .. 86 Preamble and Postamble Behavior .. 90 Preamble, Postamble Behavior in READ-To-READ Operations.

7 90 READ to READ Operations Seamless .. 90 READ to READ Operations Consecutive .. 91 Write to Write Operations Seamless .. 98 Write to Write Operations Consecutive .. 101 PRECHARGE Operation .. 105 Burst Read Operation Followed by Precharge .. 105 Burst Write Followed by Precharge .. 106 Auto Precharge .. 107 Burst READ With Auto Precharge .. 107 Burst WRITE With Auto Precharge .. 108 RAS Lock Function .. 112 Delay time from Write to Read with Auto Precharge .. 113 REFRESH Command .. 114 Micron Confidential and ProprietaryPreliminary200b: x32 Mobile LPDDR4 SDRAMPart Number Ordering InformationPDF: Rev. B 4/16 EN4 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights Requirement .. 119 SELF REFRESH Operation .. 120 Self Refresh Entry and Exit .. 120 Power-Down Entry and Exit During Self Refresh.

8 121 Command Input Timing After Power Down Exit .. 122 Self Refresh Abort .. 123 MRR, MRW, MPC Command During tXSR, tRFC .. 123 Power-Down Mode .. 126 Power-Down Entry and Exit .. 126 Input Clock Stop and Frequency Change .. 136 Clock Frequency Change CKE LOW .. 136 Clock Stop CKE LOW .. 136 Clock Frequency Change CKE HIGH .. 136 Clock Stop CKE HIGH .. 137 MODE REGISTER READ Operation .. 138 MRR after Read and Write Command .. 139 MRR after Power-Down Exit .. 141 MODE REGISTER WRITE .. 142 Mode Register Write States .. 142 VREF Current Generator (VRCG) .. 144 VREF Training .. 146 VREF(CA) Training .. 146 VREF(DQ) Training .. 151 Command Bus Training .. 156 Command Bus Training Mode .. 156 Training Sequence for Single-Rank Systems .. 157 Training Sequence for Multiple-Rank Systems .. 158 Relation between CA Input pin DQ Output pin .. 159 Write Leveling.

9 163 Mode Register Write-WR Leveling Mode .. 163 Write-Leveling Procedure: .. 163 Input Clock Frequency Stop and Change .. 164 MULTIPURPOSE Operation .. 167 Read DQ Calibration Training .. 172 Read DQ Calibration Procedure .. 172DQ Read Training Example .. 174 MPC of Read DQ Calibration after Power-Down Exit .. 175 Write Training .. 176 Internal Interval Timer .. 181 DQS Interval Oscillator Matching Error .. 183 OSC Count Readout Time .. 184 Thermal Offset .. 186 Temperature Sensor .. 186ZQ Calibration .. 187 ZQCAL Reset .. 188 Multichannel Considerations .. 189ZQ External Resistor, Tolerance, and Capacitive Loading .. 189 Frequency Set Points .. 190 Frequency set point update Timing .. 191 Pull-Up and Pull-Down Characteristics and Calibration .. 195On-Die Termination for the Command/Address Bus .. 196 ODT Mode Register and ODT State Table .. 196 Micron Confidential and ProprietaryPreliminary200b: x32 Mobile LPDDR4 SDRAMPart Number Ordering InformationPDF: Rev.

10 B 4/16 EN5 Micron Technology, Inc. reserves the right to change products or specifications without notice. 2015 Micron Technology, Inc. All rights Mode Register and ODT Characteristics .. 197 ODT for CA Update Time .. 199DQ On-Die Termination .. 199 Output Driver and Termination Register Temperature and Voltage Sensitivity .. 202 ODT Mode Register .. 203 Asynchronous ODT .. 203DQ ODT During Power-Down and Self Refresh Modes .. 205 ODT During Write Leveling Mode .. 205 TRR Mode Target Row Refresh .. 206 TRR Mode Operation .. 206 Post-Package Repair .. 208 Failed Row Address Repair .. 208 Read Preamble Training .. 210 Electrical Specifications .. 211 Absolute Maximum Ratings .. 211AC and DC Operating Conditions .. 211AC and DC Input Measurement Levels .. 213 Input Levels for CKE .. 213 Differential Input Voltage for CK .. 213 Peak Voltage Calculation Method.