20x4 LCD datasheet - Systronix

1 Systronix 20x4 LCDB rief Technical DataJuly 31, 2000 Here is brief data for the Systronix 20x4 character LCD. It is a DataVision part and uses theSamsung KS0066 LCD controller. It's a clone of the Hitachi HD44780. We're not aware of anyincompatabilities between the two - at least we have never seen any in all the code and customapplications we have 20x4 LCD is electrically and mechanically interchangeable with 20x4 LCDs from severalother vendors. The only differences we've seen among different 20x4 LCDs are:1) LED backlight brightness, voltage and current vary widely, as does the quality of the display2) There is a resistor Rf which sets the speed of the LCD interface by controlling the internaloscillator frequency. Several displays we have evaluated have a low resistor value. This makesthe display too slow. Looking at the Hitachi data sheet page 56, it appears that perhaps the incorrect resistor is really intended for 3V use of the displays.

2 At 5V the resistor Rf should be 91 Kohms. At 3V it should be 75 Kohms. Using a 3V display at5V is acceptable from a voltage standpoint (the display can operate on 3-5V) but the oscillatorwill then be running too slowly. One fix is to always check the busy flag and not use a fixed timedelay in your code, then it will work regardless of the LCD speed. The other option is to alwaysallow enough delay for the slower Systronix 20x4 LCDs have the 91 Kohm resistor and are intended for 5V you for purchasing Systronix embedded control products and accessories. If you have anyother questions please email to or phone +1-801-534-1017, fax + ABSOLUTE MAXIMUM RATINGSi ELECTRICAL CHARACTERISTICS (REFLECTIVE TYPE)ItemSymbolUnitItemSymbolConditionUn itStandard ValueStandard Voltage for LogicInput High Voltage for LCD DriverInput Low VoltageOutput High Low VoltageTopr050 CurrentTstg-2070 CIV= PIN FUNCTIONSi BLOCK DIAGRAMNoSymbolFunctionNoSymbolFunction1 VGND, 0V10DB3 Data BusSS2V+5V11DB4 DDY3 Vfor LCD Drive12DB5 EEY4 RSFunction Select13DB6Y5R/WRead/Write14DB7Y6 EEnable Signal15 LEDALED Power Supply7-9DB0-DB2 Data Bus Line16 LEDAHD44780U184 Table 4 Correspondence between Character Codes and Character Patterns (ROM Code.)

3 A00)xxxx0000xxxx0001xxxx0010xxxx0011xxxx 0100xxxx0101xxxx0110xxxx0111xxxx1000xxxx 1001xxxx1010xxxx1011xxxx1100xxxx1101xxxx 1110xxxx111100000010 0011 0100 0101 0110 01111010 1011 1100 1101 1110 1111 Upper 4 BitsLower 4 BitsCG RAM (1)(2)(3)(4)(5)(6)(7)(8)(1)(2)(3)(4)(5)( 6)(7)(8)00011000 1001 Note: The user can specify any pattern for character-generator by InstructionIf the power supply conditions for correctly operating the internal reset circuit are not met, initializationby instructions becomes to Figures 25 and 26 for the procedures on 8-bit and 4-bit initializations, onWait for more than 15 ms after VCC rises to VWait for more than msWait for more than 100 sRS 0R/W 0DB7 0DB6 0DB5 1DB4 1DB3DB2 DB1 DB0 **RS 0R/W 0DB7 0DB6 0DB5 1DB4 1DB3 DB2 DB1 DB0**RS 0R/W 0DB7 0DB6 0DB5 1DB4 1DB3 DB2 DB1**DB0*RS 0R/W 0DB7 0DB6 0DB5 1DB4 1DB3 NDB2 FDB1 DB0**0 0 00 0 00 0 00 0 00 0 00 0 01 0 00 0 10 0 I/D0 1 SInitialization endsBF cannot be checked before this instruction.

4 Function set (Interface is 8 bits long.)BF cannot be checked before this instruction. Function set (Interface is 8 bits long.)BF cannot be checked before this instruction. Function set (Interface is 8 bits long.)BF can be checked after the following instructions. When BF is not checked, the waiting time between instructions is longer than the execution instuction time. (See Table 6.)Function set (Interface is 8 bits long. Specify the number of display lines and character font.) The number of display lines and character font cannot be changed after this off Display clear Entry mode setWait for more than 40 ms after VCC rises to VFigure 25 8-Bit InterfaceHD44780U190 Reset FunctionInitializing by Internal Reset CircuitAn internal reset circuit automatically initializes the HD44780U when the power is turned on. Thefollowing instructions are executed during the initialization. The busy flag (BF) is kept in the busy stateuntil the initialization ends (BF = 1).

5 The busy state lasts for 10 ms after VCC rises to Display clear2. Function set:DL = 1; 8-bit interface dataN = 0; 1-line displayF = 0; 5 8 dot character font3. Display on/off control:D = 0; Display offC = 0; Cursor offB = 0; Blinking off4. Entry mode set:I/D = 1; Increment by 1S = 0; No shiftNote: If the electrical characteristics conditions listed under the table Power Supply Conditions UsingInternal Reset Circuit are not met, the internal reset circuit will not operate normally and will failto initialize the HD44780U. For such a case, initial-ization must be performed by the MPU asexplained in the section, Initializing by the instruction register (IR) and the data register (DR) of the HD44780U can be controlled by theMPU. Before starting the internal operation of the HD44780U, control information is temporarily storedinto these registers to allow interfacing with various MPUs, which operate at different speeds, or variousperipheral control devices.

6 The internal operation of the HD44780U is determined by signals sent fromthe MPU. These signals, which include register selection signal (RS), read/write signal (R/:), and the data bus (DB0 to DB7), make up the HD44780U instructions (Table 6). Thereare four categories of instructions that: Designate HD44780U functions, such as display format, data length, etc. Set internal RAM addresses Perform data transfer with internal RAM Perform miscellaneous functionsHD44780U191 Normally, instructions that perform data transfer with internal RAM are used the most. However, auto-incrementation by 1 (or auto-decrementation by 1) of internal HD44780U RAM addresses after each datawrite can lighten the program load of the MPU. Since the display shift instruction (Table 11) can performconcurrently with display data write, the user can minimize system development time with maximumprogramming an instruction is being executed for internal operation, no instruction other than the busyflag/address read instruction can be the busy flag is set to 1 while an instruction is being executed, check it to make sure it is 0before sending another instruction from the : Be sure the HD44780U is not in the busy state (BF = 0) before sending an instruction from theMPU to the HD44780U.

7 If an instruction is sent without checking the busy flag, the time betweenthe first instruction and next instruction will take much longer than the instruction time to Table 6 for the list of each instruc-tion execution 6 InstructionsCodeExecution Time(max) (when fcp orInstruction RSR/::DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DescriptionfOSC is 270 kHz)Cleardisplay0000000001 Clears entire display and setsDDRAM address 0 in Sets DDRAM address 0 inaddress counter. Also returnsdisplay from being shifted tooriginal position. DDRAM contents remain msEntrymode set00000001I/DSSets cursor move directionand specifies display operations areperformed during data writeand sDisplayon/offcontrol0000001 DCBSets entire display (D) on/off,cursor on/off (C), and blinkingof cursor position character(B).37 sCursor ordisplayshift000001S/C R/L Moves cursor and shiftsdisplay without changingDDRAM sFunctionset00001 DLNF Sets interface data length(DL), number of display lines(N), and character font (F).

8 37 sSetCGRAM address0001 ACG ACG ACG ACG ACG ACG Sets CGRAM data is sent andreceived after this sSetDDRAM address001 ADD ADD ADD ADD ADD ADD ADD Sets DDRAM data is sent andreceived after this sRead busyflag &address01 BFACACACACACACACR eads busy flag (BF)indicating internal operation isbeing performed and readsaddress counter sHD44780U192 Table 6 Instructions (cont)CodeExecution Time(max) (when fcp orInstruction RSR/::DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DescriptionfOSC is 270 kHz)Write datato CG orDDRAM10 Write dataWrites data into DDRAM stADD = 4 s*Read datafrom CG orDDRAM11 Read dataReads data from DDRAM stADD = 4 s*I/D = 1: IncrementI/D = 0: DecrementS= 1: Accompanies display shiftS/C = 1: Display shiftS/C = 0: Cursor moveR/L = 1: Shift to the rightR/L = 0: Shift to the leftDL = 1: 8 bits, DL = 0: 4 bitsN= 1: 2 lines, N = 0: 1 lineF= 1: 5 10 dots, F = 0: 5 8 dotsBF = 1: Internally operatingBF = 0: Instructions acceptableDDRAM: Display data RAMCGRAM: Character generatorRAMACG:CGRAM addressADD:DDRAM address(corresponds to cursoraddress)AC: Address counter used forboth DD and CGRAM addressesExecution timechanges whenfrequency changesExample:When fcp or fOSC is250 kHz,37 s = 40 s270 250 Note: indicates no effect.

9 *After execution of the CGRAM/DDRAM data write or read instruction, the RAM address counteris incremented or decremented by 1. The RAM address counter is updated after the busy flagturns off. In Figure 10, tADD is the time elapsed after the busy flag turns off until the addresscounter is stateBusy signal (DB7 pin)Address counter (DB0 to DB6 pins)tADDAA + 1 Note: t depends on the operation frequency t = (f or f ) secondsADDADDcpOSCF igure 10 Address Counter Updat