24-Bit, 20kHz, Low-Power Analog-to-Digital …

1 ADS1251. ADS. 125. 1. SBAS184D MARCH 2001 REVISED JUNE 2009. 24-Bit, 20kHz, Low-Power Analog-to-Digital converter . FEATURES DESCRIPTION. 24 BITS NO MISSING CODES The ADS1251 is a precision, wide dynamic range, delta- 19 BITS EFFECTIVE RESOLUTION UP TO sigma, Analog-to-Digital (A/D) converter with 24-bit resolu- 20kHz DATA RATE tion operating from a single +5V supply. The delta-sigma architecture features wide dynamic range, and 24 bits of no LOW NOISE: missing code performance. Effective resolution of 19 bits DIFFERENTIAL INPUTS ( of rms noise) is achieved at conversion rates up to INL: 15ppm (max) 20kHz. EXTERNAL REFERENCE ( to 5V) The ADS1251 is designed for high-resolution measurement power -DOWN MODE applications in cardiac diagnostics, smart transmitters, indus- trial process control, weigh scales, chromatography, and SYNC MODE.

2 Portable instrumentation. The converter includes a flexible, LOW power : 8mW at 20kHz 2-wire synchronous serial interface for low-cost isolation. 5mW at 10kHz The ADS1251 is a single-channel converter and is offered in an SO-8 package. It is pin-compatible with the faster ADS1252. APPLICATIONS ( data rate). CARDIAC DIAGNOSTICS. DIRECT THERMOCOUPLE INTERFACES. BLOOD ANALYSIS. INFRARED PYROMETERS. LIQUID/GAS CHROMATOGRAPHY. PRECISION PROCESS CONTROL. ADS1251. VREF. CLK. +VIN 4th-Order digital Serial SCLK.. Filter Interface DOUT/DRDY. VIN Modulator +VDD. GND. Control Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

3 All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Copyright 2001-2009, Texas Instruments Incorporated Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. ABSOLUTE MAXIMUM RATINGS(1) ELECTROSTATIC. analog Input: Current .. 100mA, Momentary 10mA, Continuous DISCHARGE SENSITIVITY. Voltage .. GND to VDD + VDD to GND .. to 6V This integrated circuit can be damaged by ESD. Texas VREF Voltage to GND .. to VDD + Instruments recommends that all integrated circuits be handled digital Input Voltage to GND.

4 To VDD + digital Output Voltage to GND .. to VDD + with appropriate precautions. Failure to observe proper han- Operating Temperature .. 40 C to 85 C dling and installation procedures can cause damage. power Dissipation .. 500mW. ESD damage can range from subtle performance degrada- NOTE: (1) Stresses above those listed under Absolute Maximum Ratings tion to complete device failure. Precision integrated circuits may cause permanent damage to the device. Exposure to absolute maximum may be more susceptible to damage because very small conditions for extended periods may affect device reliability. parametric changes could cause the device not to meet its published specifications.

5 PACKAGE/ORDERING INFORMATION(1). SPECIFIED. PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT. PRODUCT PACKAGE-LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY. ADS1251 SO-8 D 40 C to +85 C ADS1251U ADS1251U Rails, 100. " " " " " ADS1251U/2K5 Tape and Reel, 2500. NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at PRODUCT FAMILY. PRODUCT # OF INPUTS MAXIMUM DATA RATE COMMENTS. ADS1250 1 Differential Includes PGA from 1 to 8. ADS1251 1 Differential ADS1252 1 Differential ADS1253 4 Differential ADS1254 4 Differential Includes Separate analog and digital Supplies ELECTRICAL CHARACTERISTICS.

6 All specifications at TMIN to TMAX, VDD = +5V, CLK = 8 MHz, and VREF = , unless otherwise specified. ADS1251U. PARAMETER CONDITIONS MIN TYP MAX UNITS. analog INPUT. Full-Scale Input Voltage +VIN ( VIN) VREF V. Absolute Input Voltage +VIN or VIN to GND VDD V. Differential Input Impedance CLK = 430 M . CLK = 1 MHz M . CLK = 8 MHz 210 k . Input Capacitance 6 pF. Input Leakage At +25 C 5 50 pA. At TMIN to TMAX 1 nA. DYNAMIC CHARACTERISTICS. Data Rate kHz Bandwidth 3dB, CLK = 8 MHz kHz Serial Clock (SCLK) 8 MHz System Clock Input (CLK) 8 MHz ACCURACY. Integral Nonlinearity Differential Input % of FSR. THD 1kHz Input; below FS 105 dB.

7 Noise ppm of FSR, rms Resolution 24 Bits No Missing Codes 24 Bits Common-Mode Rejection 60Hz, AC 90 98 dB. Gain Error 1 % of FSR. Offset Error 30 100 ppm of FSR. Gain Sensitivity to VREF 1:1. power -Supply Rejection Ratio 70 80 dB. PERFORMANCE OVER TEMPERATURE. Offset Drift ppm/ C. Gain Drift ppm/ C. 2. ADS1251. SBAS184D. ELECTRICAL CHARACTERISTICS (Cont.). All specifications at TMIN to TMAX, VDD = +5V, CLK = 8 MHz, and VREF = , unless otherwise specified. ADS1251U. PARAMETER CONDITIONS MIN TYP MAX UNITS. VOLTAGE REFERENCE. VREF VDD V. Load Current 32 A. digital INPUT/OUTPUT. Logic Family CMOS. Logic Level: VIH + +VDD + V. VIL + V.

8 VOH IOH = 500 A + V. VOL IOL = 500 A V. Input (SCLK, CLK) Hysteresis V. Data Format Offset Binary Two's Complement power -SUPPLY REQUIREMENTS. Operation + +5 + VDC. Quiescent Current VDD = +5 VDC 2 mA. Operating power 10 mW. power -Down Current 1 A. TEMPERATURE RANGE. Operating 40 +85 C. Storage 60 +100 C. PIN CONFIGURATION PIN DESCRIPTIONS. Top View SO PIN NAME PIN DESCRIPTION. 1 +VIN analog Input: Positive Input of the Differen- tial analog Input 2 VIN analog Input: Negative Input of the Differ- ential analog Input. 3 +VDD Input: power -Supply Voltage, +5V. 4 CLK digital Input: Device System Clock. The system clock is in the form of a CMOS- compatible clock.

9 This is a Schmitt-Trigger +VIN 1 8 VREF input. 5 DOUT/DRDY digital Output: Serial Data Output/Data Ready. This output indicates that a new VIN 2 7 GND output word is available from the ADS1251. ADS1251U data output register. The serial data is +VDD 3 6 SCLK clocked out of the serial data output shift register using SCLK. 6 SCLK digital Input: Serial Clock. The serial clock CLK 4 5 DOUT/DRDY. is in the form of a CMOS-compatible clock. The serial clock operates independently from the system clock, therefore, it is pos- sible to run SCLK at a higher frequency than CLK. The normal state of SCLK is LOW. Holding SCLK HIGH will either ini- tiate a modulator reset for synchronizing multiple converters or enter power -down mode.

10 This is a Schmitt-Trigger input. 7 GND Input: Ground 8 VREF analog Input: Reference Voltage Input ADS1251 3. SBAS184D TYPICAL CHARACTERISTICS. At TA = +25 C, VDD = +5V, CLK = 8 MHz, and VREF = , unless otherwise specified. RMS NOISE vs DATA RATE EFFECTIVE RESOLUTION vs DATA OUTPUT RATE. Effective Resolution (Bits). RMS Noise (ppm of FS). 0 10 100 1k 10k 100k 100 1k 10k 100k Data Rate (Hz) Data Output Rate (Hz). RMS NOISE vs TEMPERATURE EFFECTIVE RESOLUTION vs TEMPERATURE. Effective Resolution (Bits). RMS Noise (ppm of FS). 40 20 0 20 40 60 80 100 40 20 0 20 40 60 80 100. Temperature ( C) Temperature ( C). RMS NOISE vs VREF VOLTAGE RMS NOISE vs VREF VOLTAGE.