256 10 FPGA IP User Guide - Intel FPGA and SoC

1 External Memory Interfaces Intel Stratix 10 FPGA IP User GuideUpdated for Intel Quartus Prime Design Suite: FeedbackUG-S10 EMI | document on the web: PDF | HTMLC ontents1. External Memory Interfaces Intel Stratix 10 FPGA IP Intel Stratix 10 EMIF IP Design Intel Stratix 10 EMIF IP Design Intel Stratix 10 EMIF IP Product Intel Stratix 10 EMIF Architecture: Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: I/O Intel Stratix 10 EMIF Architecture: Input DQS Clock Intel Stratix 10 EMIF Architecture: PHY Clock Intel Stratix 10 EMIF Architecture.

2 PLL Reference Clock Intel Stratix 10 EMIF Architecture: Clock Phase Intel Stratix 10 EMIF Intel Stratix 10 EMIF DQS Intel Stratix 10 EMIF Intel Stratix 10 Calibration Stages .. Intel Stratix 10 Calibration Stages Intel Stratix 10 Calibration Intel Stratix 10 Calibration Intel Stratix 10 EMIF IP Hard Memory Intel Stratix 10 Hard Memory Controller Rate Conversion Hardware Resource Sharing Among Multiple Intel Stratix 10 I/O SSM I/O Bank PLL Reference Clock Core Clock Network User-requested Reset in Intel Stratix 10 EMIF Intel Stratix 10 EMIF for Hard Processor Restrictions on I/O Bank Usage for Intel Stratix 10 EMIF IP with Using the EMIF Debug Toolkit with Intel Stratix 10 HPS Intel Stratix 10 EMIF Ping Pong Intel Stratix

3 10 Ping Pong PHY Feature Intel Stratix 10 Ping Pong PHY Intel Stratix 10 Ping Pong PHY Intel Stratix 10 Ping Pong PHY Using the Ping Pong Ping Pong PHY Simulation Example 463. Intel Stratix 10 EMIF IP End-User Interface and Signal Intel Stratix 10 EMIF IP Interfaces for Intel Stratix 10 EMIF IP Interfaces for Intel Stratix 10 EMIF IP Interfaces for QDR II/II+/II+ Intel Stratix 10 EMIF IP Interfaces for Memory Interfaces Intel Stratix 10 FPGA IP User GuideSend Intel Stratix 10 EMIF IP Interfaces for RLDRAM AFI AFI Clock and Reset AFI Address and Command AFI Write Data AFI Read Data AFI Calibration Status AFI Tracking Management AFI Shadow Register Management AFI Timing AFI Address and Command Timing AFI Write

4 Sequence Timing AFI Read Sequence Timing AFI Calibration Status Timing Intel Stratix 10 Memory Mapped Register (MMR) ecc3: ECC Error and Interrupt ecc4: Status and Error ecc5: Address of Most Recent ecc6: Address of Most Recent Correction Command ecc7: Extension for Address of Most Recent ecc8: Extension for Address of Most Recent Correction Command FeedbackExternal Memory Interfaces Intel Stratix 10 FPGA IP User Guide34. Intel Stratix 10 EMIF Simulating Memory Simulation Simulation Calibration Abstract PHY Simulation Functional Simulation with Verilog Functional Simulation with Simulating the Design Intel Stratix 10 EMIF IP for Parameter Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters: FPGA Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters: Mem Intel Stratix 10 EMIF IP DDR3 Parameters: Mem Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters.

5 Intel Stratix 10 EMIF IP DDR3 Parameters: Intel Stratix 10 EMIF IP DDR3 Parameters: Example Board Skew Equations for DDR3 Board Skew Pin and Resource Interface FPGA Pin Guidelines for Intel Stratix 10 EMIF DDR3 Board Design Terminations for DDR3 and DDR4 with Intel Stratix 10 Channel Signal Integrity Layout Design Layout Package 1836. Intel Stratix 10 EMIF IP for Parameter Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: FPGA Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: Mem Intel Stratix 10 EMIF IP DDR4 Parameters: Mem Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters: Intel Stratix 10 EMIF IP DDR4 Parameters.

6 Example Board Skew Equations for DDR4 Board Skew Pin and Resource Interface FPGA Pin Guidelines for Intel Stratix 10 EMIF Memory Interfaces Intel Stratix 10 FPGA IP User GuideSend Resource Sharing Guidelines (Multiple Interfaces).. DDR4 Board Design Terminations for DDR3 and DDR4 with Intel Stratix 10 Channel Signal Integrity Layout Design Layout Package 2407. Intel Stratix 10 EMIF IP for QDR II/II+/II+ Parameter Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: FPGA Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Mem Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters: Intel Stratix 10 EMIF IP QDR II/II+/II+ Xtreme Parameters.

7 Board Skew Equations for QDRII, QDRII+, and QDRII+ Xtreme Board Skew Pin and Resource Interface QDR II/II+/II+ Xtreme Board Design QDR II SRAM General Layout QDR II Layout QDR II SRAM Layout Package 2728. Intel Stratix 10 EMIF IP for Parameter Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: FPGA Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: Mem Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters: Intel Stratix 10 EMIF IP QDR-IV Parameters.

8 Example Board Skew Equations for QDR-IV Board Skew Pin and Resource Interface QDR-IV Board Design QDR-IV Layout General Layout QDR-IV Layout Package 3009. Intel Stratix 10 EMIF IP for RLDRAM Parameter FeedbackExternal Memory Interfaces Intel Stratix 10 FPGA IP User Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: FPGA Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Mem Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Intel Stratix 10 EMIF IP RLDRAM 3 Parameters: Intel Stratix 10 EMIF IP RLDRAM 3 Parameters.

9 Example Board Skew Equations for RLDRAM 3 Board Skew Pin and Resource Interface RLDRAM 3 Board Design RLDRAM 3 General Layout RLDRAM 3 Layout Layout Package 33110. Intel Stratix 10 EMIF IP Timing Timing Closure .. Timing Timing Report Optimizing Early I/O Timing Performing Early I/O Timing 34111. Optimizing Controller Interface Bank Management Data Improving Controller Auto-Precharge Bank Additive Latency and Bank User-Controlled Frequency of Series of Reads or Data Starvation Command Enable Command Priority Intel Stratix 10 EMIF IP Interface Configuration Performance Interface Configuration Bottleneck and Efficiency Functional Issue Intel IP Memory Vendor Memory Memory Interfaces Intel Stratix 10 FPGA IP User GuideSend Transcript Window Modifying the Example Driver to Replicate the Timing Issue Evaluating FPGA

10 Timing Evaluating External Memory Interface Timing Verifying Memory IP Using the Signal Tap II Logic Signals to Monitor with the Signal Tap II Logic Hardware Debugging Create a Simplified Design that Demonstrates the Same Measure Power Distribution Measure Signal Integrity and Setup and Hold Vary Operate at a Lower Determine Whether the Issue Exists in Previous Versions of Determine Whether the Issue Exists in the Current Version of Try A Different Try Other Debugging Categorizing Hardware Signal Integrity Hardware and Calibration Debugging Intel Stratix 10 EMIF External Memory Interface Debug On-Chip Debug for Intel Stratix Configuring Your EMIF IP for Use with the Debug Example Tcl Script for Running the EMIF Debug Using the EMIF Debug Toolkit with Intel Stratix 10 HPS Intel Stratix 10 EMIF Debugging User Setup and On-Chip Debug Port for Intel Stratix 10 EMIF EMIF On-Chip Debug Access On-Die Termination Calibration.