256 KBIT (32KB X8) UV EPROM AND OTP EPROM

1 M27C256B. 256 Kbit (32Kb x 8) UV EPROM and OTP EPROM . 5V 10% SUPPLY VOLTAGE in READ. OPERATION. ACCESS TIME: 45ns LOW POWER CONSUMPTION: Active Current 30mA at 5 MHz 28 28. Standby Current 100 A. 1 1. PROGRAMMING VOLTAGE: PROGRAMMING TIME: 100 s/word FDIP28W (F) PDIP28 (B). ELECTRONIC SIGNATURE. Manufacturer Code: 20h Device Code: 8Dh DESCRIPTION. The M27C256B is a 256 Kbit EPROM offered in PLCC32 (C) TSOP28 (N). the two ranges UV (ultra violet erase) and OTP 8 x mm (one time programmable). It is ideally suited for mi- croprocessor systems and is organized as 32,768. by 8 bits. Figure 1. Logic Diagram The FDIP28W (window ceramic frit-seal package). has a transparent lid which allows the user to ex- pose the chip to ultraviolet light to erase the bit pat- tern. A new pattern can then be written to the device by following the programming procedure.

2 VCC VPP. For applications where the content is programmed only one time and erasure is not required, the M27C256B is offered in PDIP28, PLCC32 and 15 8. TSOP28 (8 x mm) packages. A0-A14 Q0-Q7. E M27C256B. G. VSS. AI00755B. August 2002 1/16. M27C256B. Figure 2A. DIP Connections Figure 2B. LCC Connections VCC. VPP. A12. A14. A13. VPP 1 28 VCC. DU. A7. A12 2 27 A14. A7 3 26 A13 1 32. A6 4 25 A8 A6 A8. A5 5 24 A9 A5 A9. 6 23 A11 A4 A11. A4. A3 7 22 G A3 NC. M27C256B A2 9 M27C256B 25 G. A2 8 21 A10. 9 20 E A1 A10. A1. A0 10 19 Q7 A0 E. Q0 11 18 Q6 NC Q7. Q1 12 17 Q5 Q0 Q6. 17. Q2 13 16 Q4. Q1. Q2. VSS. DU. Q3. Q4. Q5. VSS 14 15 Q3. AI00756. AI00757. Figure 2C. TSOP Connections Table 1. Signal Names A0-A14 Address Inputs Q0-Q7 Data Outputs G 22 21 A10 E Chip Enable A11 E. G Output Enable A9 Q7. A8 Q6 VPP Program Supply A13 Q5.

3 A14 Q4 VCC Supply Voltage VCC 28 15 Q3. M27C256B VSS Ground VPP 1 14 VSS. A12 Q2 NC Not Connected Internally A7 Q1. DU Don't Use A6 Q0. A5 A0. A4 A1. A3 7 8 A2. AI00614B. 2/16. M27C256B. Table 2. Absolute Maximum Ratings (1). Symbol Parameter Value Unit TA Ambient Operating Temperature (3) 40 to 125 C. TBIAS Temperature Under Bias 50 to 125 C. TSTG Storage Temperature 65 to 150 C. VIO (2) Input or Output Voltage (except A9) 2 to 7 V. VCC Supply Voltage 2 to 7 V. VA9 (2) A9 Voltage 2 to V. VPP Program Supply Voltage 2 to 14 V. Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied.

4 Exposure to Absolute Maximum Rating condi- tions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant qual- ity documents. 2. Minimum DC voltage on Input or Output is with possible undershoot to for a period less than 20ns. Maximum DC. voltage on Output is VCC + with possible overshoot to VCC +2V for a period less than 20ns. 3. Depends on range. Table 3. Operating Modes Mode E G A9 VPP Q7-Q0. Read VIL VIL X VCC Data Out Output Disable VIL VIH X VCC Hi-Z. Program VIL Pulse VIH X VPP Data In Verify VIH VIL X VPP Data Out Program Inhibit VIH VIH X VPP Hi-Z. Standby VIH X X VCC Hi-Z. Electronic Signature VIL VIL VID VCC Codes Note: X = VIH or VIL, VID = 12V Table 4. Electronic Signature Identifier A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 Hex Data Manufacturer's Code VIL 0 0 1 0 0 0 0 0 20h Device Code VIH 1 0 0 0 1 1 0 1 8Dh 3/16.

5 M27C256B. Table 5. AC Measurement Conditions High Speed Standard Input Rise and Fall Times 10ns 20ns Input Pulse Voltages 0 to 3V to Input and Output Timing Ref. Voltages and 2V. Figure 3. AC Testing Input Output Waveform Figure 4. AC Testing Load Circuit High Speed 3V 1N914. 0V . DEVICE. Standard UNDER OUT. TEST. CL. CL = 30pF for High Speed AI01822. CL = 100pF for Standard CL includes JIG capacitance AI01823B. Table 6. Capacitance (1) (TA = 25 C, f = 1 MHz). Symbol Parameter Test Condition Min Max Unit CIN Input Capacitance VIN = 0V 6 pF. COUT Output Capacitance VOUT = 0V 12 pF. Note: 1. Sampled only, not 100% tested. DEVICE OPERATION dresses are stable, the address access time The operating modes of the M27C256B are listed (tAVQV) is equal to the delay from E to output in the Operating Modes. A single power supply is (tELQV).

6 Data is available at the output after delay required in the read mode. All inputs are TTL lev- of tGLQV from the falling edge of G, assuming that els except for VPP and 12V on A9 for Electronic E has been low and the addresses have been sta- Signature. ble for at least tAVQV-tGLQV. Read Mode Standby Mode The M27C256B has two control functions, both of The M27C256B has a standby mode which reduc- which must be logically active in order to obtain es the supply current from 30mA to 100 A. The data at the outputs. Chip Enable (E) is the power M27C256B is placed in the standby mode by ap- control and should be used for device selection. plying a CMOS high signal to the E input. When in Output Enable (G) is the output control and should the standby mode, the outputs are in a high imped- be used to gate data to the output pins, indepen- ance state, independent of the G input.

7 Dent of device selection. Assuming that the ad- 4/16. M27C256B. Table 7. Read Mode DC Characteristics (1). (TA = 0 to 70 C, 40 to 85 C, 40 to 105 C or 40 to 125 C; VCC = 5V 5% or 5V 10%; VPP = VCC). Symbol Parameter Test Condition Min Max Unit ILI Input Leakage Current 0V VIN VCC 10 A. ILO Output Leakage Current 0V VOUT VCC 10 A. E = VIL, G = VIL, ICC Supply Current 30 mA. IOUT = 0mA, f = 5 MHz ICC1 Supply Current (Standby) TTL E = VIH 1 mA. ICC2 Supply Current (Standby) CMOS E > VCC 100 A. IPP Program Current VPP = VCC 100 A. VIL Input Low Voltage V. VIH (2) Input High Voltage 2 VCC + 1 V. VOL Output Low Voltage IOL = V. Output High Voltage TTL IOH = 1mA V. VOH. Output High Voltage CMOS IOH = 100 A VCC V. Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

8 2. Maximum DC voltage on Output is VCC + Table 8A. Read Mode AC Characteristics (1). (TA = 0 to 70 C, 40 to 85 C, 40 to 105 C or 40 to 125 C; VCC = 5V 5% or 5V 10%; VPP = VCC). M27C256B. Symbol Alt Parameter Test Condition -45 (3) -60 -70 -80 Unit Min Max Min Max Min Max Min Max Address Valid to tAVQV tACC E = VIL, G = VIL 45 60 70 80 ns Output Valid Chip Enable Low to tELQV tCE G = VIL 45 60 70 80 ns Output Valid Output Enable Low to tGLQV tOE E = VIL 25 30 35 40 ns Output Valid Chip Enable High to tEHQZ (2) tDF. Output Hi-Z. G = VIL 0 25 0 30 0 30 0 30 ns Output Enable High tGHQZ (2) tDF. to Output Hi-Z. E = VIL 0 25 0 30 0 30 0 30 ns Address Transition to tAXQX tOH E = VIL, G = VIL 0 0 0 0 ns Output Transition Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.

9 2. Sampled only, not 100% tested. 3. Speed obtained with High Speed AC measurement conditions. Two Line Output Control For the most efficient use of these two control Because EPROMs are usually used in larger lines, E should be decoded and used as the prima- memory arrays, this product features a 2 line con- ry device selecting function, while G should be trol function which accommodates the use of mul- made a common connection to all devices in the tiple memory connection. The two line control array and connected to the READ line from the function allows: system control bus. This ensures that all deselect- ed memory devices are in their low power standby a. the lowest possible memory power dissipation, mode and that the output pins are only active b. complete assurance that output bus contention when data is desired from a particular memory de- will not occur.

10 Vice. 5/16. M27C256B. Table 8B. Read Mode AC Characteristics (1). (TA = 0 to 70 C, 40 to 85 C, 40 to 105 C or 40 to 125 C; VCC = 5V 5% or 5V 10%; VPP = VCC). M27C256B. Symbol Alt Parameter Test Condition -90 -10 -12 -15/-20/-25 Unit Min Max Min Max Min Max Min Max Address Valid to tAVQV tACC E = VIL, G = VIL 90 100 120 150 ns Output Valid Chip Enable Low to tELQV tCE G = VIL 90 100 120 150 ns Output Valid Output Enable Low to tGLQV tOE E = VIL 40 50 60 65 ns Output Valid Chip Enable High to tEHQZ (2) tDF. Output Hi-Z. G = VIL 0 30 0 30 0 40 0 50 ns Output Enable High tGHQZ (2) tDF. to Output Hi-Z. E = VIL 0 30 0 30 0 40 0 50 ns Address Transition to tAXQX tOH E = VIL, G = VIL 0 0 0 0 ns Output Transition Note: 1. VCC must be applied simultaneously with or before VPP and removed simultaneously or after VPP.