256K x 16 HIGH SPEED ASYNCHRONOUS CMOS …

1 Integrated Silicon Solution, Inc. 1 Rev. H102/10/2017 Copyright 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-est version of this device specification before relying on any published information and before placing orders for products. Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness.

2 Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:a.) the risk of injury or damage has been minimized;b.) the user assume all such risks; andc.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances IS61WV25616 ALL/ALSIS61WV25616 BLL/BLSIS64WV25616 BLL/BLSFEATURESHIGH SPEED : (IS61/64WV25616 ALL/BLL) high - SPEED access time: 8, 10, 20 ns Low Active Power: 85 mW (typical) Low Standby Power: 7 mW (typical) cmos standbyLOW POWER: (IS61/64WV25616 ALS/BLS) high - SPEED access time: 25, 35, 45 ns Low Active Power: 35 mW (typical) Low Standby Power: mW (typical) cmos standby Single power supply Vdd to (IS61WV25616 Axx) Vdd to (IS61/64WV25616 Bxx) Fully static operation.

3 No clock or refresh required Three state outputs Data control for upper and lower bytes Industrial and Automotive temperature support Lead-free available256K x 16 high SPEED ASYNCHRONOUS cmos STATIC RAM DESCRIPTIONThe ISSI IS61WV25616 Axx/Bxx and IS64WV25616 Bxx are high - SPEED , 4,194,304-bit static RAMs organized as 262,144 words by 16 bits. It is fabricated using ISSI's high -performance cmos technology. This highly reliable process coupled with innovative circuit design techniques, yields high -performance and low power consumption CE is high (deselected), the device assumes a standby mode at which the power dissipation can be re-duced down with cmos input memory expansion is provided by using Chip Enable and Output Enable inputs, CE and OE.

4 The active LOW Write Enable (WE) controls both writing and reading of the memory. A data byte allows Upper Byte (UB) and Lower Byte (LB) IS61WV25616 Axx/Bxx and IS64WV25616 Bxx are packaged in the JEDEC standard 44-pin 400mil SOJ, 44-pin TSOP Type II and 48-pin Mini BGA (6mm x 8mm).FUNCTIONAL BLOCK DIAGRAMA0-A17 CEOEWE256K x 16 MEMORY ARRAYDECODERCOLUMN I/OCONTROLCIRCUITGNDVDDI/ODATACIRCUITI/O 0-I/O7 Lower ByteI/O8-I/O15 Upper ByteUBLBFEBRUARY 20172 Integrated Silicon Solution, Inc. H102/10/2017IS61WV25616 ALL/ALS, IS61WV25616 BLL/BLS, IS64WV25616 BLL/BLSTRUTH TABLE I/O PIN Mode WE CE OE LB UB I/O0-I/O7 I/O8-I/O15 VDD Current Not Selected X H X X X high -Z high -Z Isb1.

5 Isb2 Output Disabled H L H X X high -Z high -Z Icc X L X H H high -Z high -Z Read H L L L H dout high -Z Icc H L L H L high -Z dout H L L L L dout dout Write L L X L H dIn high -Z Icc L L X H L high -Z dIn L L X L L dIn dInPIN DESCRIPTIONSA0-A17 Address InputsI/O0-I/O15 Data Inputs/OutputsCE Chip Enable InputOE Output Enable InputWE Write Enable InputLB Lower-byte Control (I/O0-I/O7)UB Upper-byte Control (I/O8-I/O15)NC No ConnectionVdd PowerGND Ground1234567891011121314151617181920212 2444342414039383736353433323130292827262 52423A0A1A2A3A4 CEI/O0I/O1I/O2I/O3 VDDGNDI/O4I/O5I/O6I/O7 WEA5A6A7A8A9A17A16A15 OEUBLBI/O15I/O14I/O13I/O12 GNDVDDI/O11I/O10I/O9I/O8 NCA14A13A12A11A10 PIN CONFIGURATIONS44-Pin TSOP (Type II) and SOJ *soJ package under Silicon Solution, Inc.

6 3 Rev. H102/10/2017IS61WV25616 ALL/ALS, IS61WV25616 BLL/BLS, IS64WV25616 BLL/BLS123456789101133323130292827262524 2312131415161718192021224443424140393837 363534 CEI/O0I/O1I/O2I/O3 VDDGNDI/O4I/O5I/O6I/O7I/O15I/O14I/O13I/O 12 GNDVDDI/O11I/O10I/O9I/O8 NCTOP VIEWWEA0A1A2A3A4A5A6A7A8A9A17A16A15A14A1 3A12A11A10 OEUBLB1 2 3 4 5 6 ABCDEFGHLBOEA0A1A2N/CI/O8 UBA3A4 CEI/O0I/O9I/O10A5A6I/O1I/O2 GNDI/O11A17A7I/O3 VDDVDDI/O12 NCA16I/O4 GNDI/O14I/O13A14A15I/O5I/O6I/O15 NCA12A13 WEI/O7 NCA8A9A10A11NC48-Pin mini BGA (6mm x 8mm)PIN CONFIGURATIONS44-Pin LQFPPIN DESCRIPTIONSA0-A17 Address InputsI/O0-I/O15 Data Inputs/OutputsCE Chip Enable InputOE Output Enable InputWE Write Enable InputLB Lower-byte Control (I/O0-I/O7)UB Upper-byte Control (I/O8-I/O15)NC No ConnectionVdd PowerGND Ground*LQFP package under Integrated Silicon Solution, Inc.

7 H102/10/2017IS61WV25616 ALL/ALS, IS61WV25616 BLL/BLS, IS64WV25616 BLL/BLSDC ELECTRICAL CHARACTERISTICS (Over Operating Range)VDD = Symbol Parameter Test Conditions Min. Max. Unit VoH Output high Voltage Vdd = Min., IoH = mA V VoL Output LOW Voltage Vdd = Min., IoL = mA V VIH Input high Voltage Vdd + V VIL Input LOW Voltage(1) V ILI Input Leakage GND VIn Vdd 1 1 A ILo Output Leakage GND Vout Vdd, Outputs Disabled 1 1 ANote:1. VIL (min.) = DC; VIL (min.) = AC (pulse width < 20 ns). Not 100% tested. VIH (max.) = Vdd + dc; VIH (max.) = Vdd + Ac (pulse width < 20 ns). Not 100% ELECTRICAL CHARACTERISTICS (Over Operating Range)VDD = + 5% Symbol Parameter Test Conditions Min.

8 Max. Unit VoH Output high Voltage Vdd = Min., IoH = mA V VoL Output LOW Voltage Vdd = Min., IoL = mA V VIH Input high Voltage 2 Vdd + V VIL Input LOW Voltage(1) V ILI Input Leakage GND VIn Vdd 1 1 A ILo Output Leakage GND Vout Vdd, Outputs Disabled 1 1 ANote:1. VIL (min.) = DC; VIL (min.) = AC (pulse width < 20 ns). Not 100% tested. VIH (max.) = Vdd + dc; VIH (max.) = Vdd + Ac (pulse width < 20 ns). Not 100% ELECTRICAL CHARACTERISTICS (Over Operating Range)VDD = Symbol Parameter Test Conditions VDD Min. Max. Unit VoH Output high Voltage IoH = mA V VoL Output LOW Voltage IoL = mA V VIH Input high Voltage Vdd + V VIL(1) Input LOW Voltage V ILI Input Leakage GND VIn Vdd 1 1 A ILo Output Leakage GND Vout Vdd, Outputs Disabled 1 1 ANote:1.

9 VIL (min.) = DC; VIL (min.) = AC (pulse width < 20 ns). Not 100% tested. VIH (max.) = Vdd + dc; VIH (max.) = Vdd + Ac (pulse width < 20 ns). Not 100% Silicon Solution, Inc. 5 Rev. H102/10/2017IS61WV25616 ALL/ALS, IS61WV25616 BLL/BLS, IS64WV25616 BLL/BLSAC TEST LOADSF igure 5 pFIncludingjig andscope353 2. ZO = 50 OUTPUT30 pFIncludingjig andscopeAC TEST CONDITIONS Parameter Unit Unit Unit ( ) ( + 10%) ( ) Input Pulse Level 0V to 3V 0V to 3V 0V to Input Rise and Fall Times 1V/ ns 1V/ ns 1V/ ns Input and Output Timing and Reference Level (VRef) Output Load See Figures 1 and 2 See Figures 1 and 2 See Figures 1 and 26 Integrated Silicon Solution, Inc.

10 H102/10/2017IS61WV25616 ALL/ALS, IS61WV25616 BLL/BLS, IS64WV25616 BLL/BLSABSOLUTE MAXIMUM RATINGS(1) Symbol Parameter Value Unit Vterm Terminal Voltage with Respect to GND to Vdd + V Vdd Vdd Relates to GND to V tstg Storage Temperature 65 to +150 C Pt Power Dissipation WNotes:1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. CAPACITANCE(1,2) Symbol Parameter Conditions Max.