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2N7002K - Small Signal MOSFET - ON Semiconductor

DATA Semiconductor Components Industries, LLC, 2007 August, 2021 Rev. 181 Publication Order Number: 2N7002K /DSmall Signal MOSFET60 V, 380 mA, Single, N Channel, SOT 232N7002K, 2V7002 KFeatures ESD Protected Low RDS(on) Surface Mount Package 2V Prefix for Automotive and Other Applications Requiring UniqueSite and Control Change Requirements; AEC Q101 Qualified andPPAP Capable These Devices are Pb Free, Halogen Free/BFR Free and are RoHSCompliantApplications Low Side Load Switch Level Shift Circuits DC DC Converter Portable Applications DSC, PDA, Cell Phone, RATINGS (TJ = 25 C unless otherwise stated)RatingSymbolValueUnitDrain to Source VoltageVDSS60 VGate to Source VoltageVGS 20 VDrain Current (Note 1)Steady State 1 sq in PadTA = 25 CTA = 85 CID380270mADrain Current (Note 2)Steady State Minimum PadTA = 25 CTA = 85 CID320230mAPower DissipationSteady State 1 sq in PadSteady State Minimum PadPD420300mWPulsed Drain Current (tp = 10 ms) Junction and StorageTem

2N7002K, 2V7002K www.onsemi.com 3 TYPICAL CHARACTERISTICS 5.0 V Figure 1. On−Region Characteristics Figure 2.Transfer Characteristics VDS, DRAIN−TO−SOURCE VOLTAGE (V) VGS, GATE−TO−SOURCE VOLTAGE (V) 0 2 4 6 0 0.4 0.8 1.2 1.6 0 2 4 6 0 0.4 0.8 1.2 Figure 3.

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Transcription of 2N7002K - Small Signal MOSFET - ON Semiconductor

1 DATA Semiconductor Components Industries, LLC, 2007 August, 2021 Rev. 181 Publication Order Number: 2N7002K /DSmall Signal MOSFET60 V, 380 mA, Single, N Channel, SOT 232N7002K, 2V7002 KFeatures ESD Protected Low RDS(on) Surface Mount Package 2V Prefix for Automotive and Other Applications Requiring UniqueSite and Control Change Requirements; AEC Q101 Qualified andPPAP Capable These Devices are Pb Free, Halogen Free/BFR Free and are RoHSCompliantApplications Low Side Load Switch Level Shift Circuits DC DC Converter Portable Applications DSC, PDA, Cell Phone, RATINGS (TJ = 25 C unless otherwise stated)RatingSymbolValueUnitDrain to Source VoltageVDSS60 VGate to Source VoltageVGS 20 VDrain Current (Note 1)Steady State 1 sq in PadTA = 25 CTA = 85 CID380270mADrain Current (Note 2)Steady State Minimum PadTA = 25 CTA = 85 CID320230mAPower DissipationSteady State 1 sq in PadSteady State Minimum PadPD420300mWPulsed Drain Current (tp = 10 ms)

2 Junction and StorageTemperature RangeTJ, TSTG 55 to+150 CSource Current (Body Diode)IS300mALead Temperature for Soldering Purposes(1/8 from case for 10 s)TL260 CGate Source ESD Rating (HBM, Method 3015)ESD2000 VStresses exceeding those listed in the Maximum Ratings table may damage thedevice. If any of these limits are exceeded, device functionality should not beassumed, damage may occur and reliability may be Surface mounted on FR4 board using 1 sq in pad size with 1 oz Surface mounted on FR4 board using sq in pad size with 1 oz ORDERING INFORMATION2N7002KT1G,2V7002KT1G3000 / Tape & ReelSIMPLIFIED SCHEMATICSOT 23 CASE 318 STYLE 21704 MGGMARKING DIAGRAM& PIN ASSIGNMENT321 DrainGate213 SourceSOT 23(Pb Free)60 W @ 10 VRDS(on) MAX380 mAID MAXV(BR)

3 DSS For information on tape and reel specifications,including part orientation and tape sizes, pleaserefer to our Tape and Reel Packaging SpecificationsBrochure, BRD8011 W @ VGateSourceDrain321(Top View)704= Specific Device Code*M= Date Code*G= Pb Free Package2N7002KT7G3500 / Tape & ReelSOT 23(Pb Free)*Specific Device Code, Date Code or overbarorientation and/or location may vary depend-ing upon manufacturing location. This is arepresentation only and actual devices maynot match this drawing exactly.(Note: Microdot may be in either location) 2N7002K , CHARACTERISTICSC haracteristicSymbolMaxUnitJunction to Ambient Steady State (Note 3)RqJA300 C/WJunction to Ambient t 5 s (Note 3)92 Junction to Ambient Steady State (Note 4)417 Junction to Ambient t 5 s (Note 4)1543.

4 Surface mounted on FR4 board using 1 sq in pad size with 1 oz Surface mounted on FR4 board using sq in pad size with 1 oz CHARACTERISTICS (TJ = 25 C unless otherwise specified)ParameterSymbolTest ConditionMinTypMaxUnitOFF CHARACTERISTICSD rain to Source Breakdown VoltageV(BR)DSSVGS = 0 V, ID = 250 mA60 VDrain to Source Breakdown VoltageTemperature CoefficientV(BR)DSS/TJ71mV/ CZero Gate Voltage Drain CurrentIDSSVGS = 0 V,VDS = 60 VTJ = 25 C1mATJ = 125 C10 VGS = 0 V,VDS = 50 VTJ = 25 C100nAGate to Source Leakage CurrentIGSSVDS = 0 V, VGS = 20 V 10mAVDS = 0 V, VGS = 10 V450nAVDS = 0 V, VGS = V150nAON CHARACTERISTICS (Note 5)Gate Threshold VoltageVGS(TH)VGS = VDS, ID = 250 Threshold TemperatureCoefficientVGS(TH) CDrain to Source On ResistanceRDS(on)VGS = 10 V, ID = 500 = V, ID = 200 TransconductancegFSVDS = 5 V, ID = 200 mA530mSCHARGES AND CAPACITANCESI nput CapacitanceCISSVGS = 0 V, f = 1 MHz,VDS = 20 Transfer Gate ChargeQG(TOT)VGS = V, VDS = 10 V.

5 ID = 200 Gate ChargeQG(TH) to Source to Drain CHARACTERISTICS, VGS = V (Note 6)Turn On Delay Timetd(ON)VGS = 10 V, VDD = 25 V,ID = 500 mA, RG = 25 Off Delay Timetd(OFF) Timetf29 DRAIN SOURCE DIODE CHARACTERISTICSF orward Diode VoltageVSDVGS = 0 V,IS = 200 mATJ = 25 = 85 parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Productperformance may not be indicated by the Electrical Characteristics if operated under different Pulse Test: pulse width 300 ms, duty cycle 2%6. Switching characteristics are independent of operating junction temperatures2N7002K, VFigure 1.

6 On Region CharacteristicsFigure 2. Transfer CharacteristicsVDS, DRAIN TO SOURCE VOLTAGE (V)VGS, GATE TO SOURCE VOLTAGE (V) 3. On Resistance vs. Drain Current andTemperatureFigure 4. On Resistance vs. Drain Current andTemperatureID, DRAIN CURRENT (A) 5. On Resistance vs. Gate to SourceVoltageFigure 6. On Resistance Variation withTemperatureVGS, GATE TO SOURCE VOLTAGE (V)TJ, JUNCTION TEMPERATURE ( C) 25 , DRAIN CURRENT (A)ID, DRAIN CURRENT (A)RDS(on), DRAIN TO SOURCE RESISTANCE (W)RDS(on), DRAIN TO SOURCE RESISTANCE (W)RDS(on), DRAIN TO SOURCERESISTANCE (NORMALIZED)VGS = 10 VTJ = 55 CTJ = 125 CTJ = 25 CTJ = 55 CTJ = 125 CTJ = 25 CTJ = 85 CVGS = VID, DRAIN CURRENT (A) (on), DRAIN TO SOURCE RESISTANCE (W)TJ = 55 CTJ = 125 CTJ = 25 CTJ = 85 CVGS = 10 VID = 500 mAID = 200 mA150ID = AVGS = VVGS = 10 , CHARACTERISTICSF igure 7.

7 Capacitance VariationFigure 8. Gate to Source andDrain to Source Voltage vs. Total ChargeQg, TOTAL GATE CHARGE (nC) 9. Diode Forward Voltage vs. CurrentVSD, SOURCE TO DRAIN VOLTAGE (V) , GATE TO SOURCE VOLTAGE (V)IS, SOURCE CURRENT (A)TJ = 25 CID = A2016128400102030C, CAPACITANCE (pF)CissCossCrssTJ = 25 CVGS = 0 VGATE TO SOURCE OR DRAIN TO SOURCE VOLTAGE (V)TJ = 25 CTJ = 85 CVGS = 0 10. Threshold Voltage withTemperatureTJ, JUNCTION TEMPERATURE ( C)1251007550250 25 (TH), THRESHOLD VOLTAGE (V)150ID = 250 , 11. Thermal Response 1 sq in padt, PULSE TIME (s)RqJA(t) ( C/W) EFFECTIVE TRANSIENTTHERMAL Cycle = 12. Thermal Response minimum padt, PULSE TIME (s)RqJA(t) ( C/W) EFFECTIVE TRANSIENTTHERMAL Cycle = 23 (TO 236)CASE 318 08 ISSUE ASDATE 30 JAN 2018 SCALE 4:1DA13121 XXXMGGXXX = Specific Device CodeM= Date CodeG= Pb Free Package*This information is generic.

8 Please refer todevice data sheet for actual part Free indicator, G or microdot G ,may or may not be DIAGRAM*NOTES:1. DIMENSIONING AND TOLERANCING PER ASME , CONTROLLING DIMENSION: MAXIMUM LEAD THICKNESS INCLUDES LEAD LEAD THICKNESS IS THE MINIMUM THICKNESS OFTHE BASE DIMENSIONS D AND E DO NOT INCLUDE MOLD FLASH,PROTRUSIONS, OR GATE FOOTPRINTVIEW VIEW 22:PIN 1. RETURN2. OUTPUT3. INPUTSTYLE 6:PIN 1. BASE2. EMITTER3. COLLECTORSTYLE 7:PIN 1. EMITTER2. BASE3. COLLECTORSTYLE 8:PIN 1. ANODE2. NO CONNECTION3. CATHODESTYLE 9:PIN 1. ANODE2. ANODE3. CATHODESTYLE 10:PIN 1. DRAIN2. SOURCE3. GATESTYLE 11:PIN 1.

9 ANODE2. CATHODE3. CATHODE ANODESTYLE 12:PIN 1. CATHODE2. CATHODE3. ANODESTYLE 13:PIN 1. SOURCE2. DRAIN3. GATESTYLE 14:PIN 1. CATHODE2. GATE3. ANODESTYLE 15:PIN 1. GATE2. CATHODE3. ANODESTYLE 16:PIN 1. ANODE2. CATHODE3. CATHODESTYLE 17:PIN 1. NO CONNECTION2. ANODE3. CATHODESTYLE 18:PIN 1. NO CONNECTION2. CATHODE3. ANODESTYLE 19:PIN 1. CATHODE2. ANODE3. CATHODE ANODESTYLE 23:PIN 1. ANODE2. ANODE3. CATHODESTYLE 20:PIN 1. CATHODE2. ANODE3. GATESTYLE 21:PIN 1. GATE2. SOURCE3. DRAINSTYLE 1 THRU 5:CANCELLEDSTYLE 24:PIN 1. GATE 2. DRAIN 3. SOURCESTYLE 25:PIN 1. ANODE 2. CATHODE 3.

10 GATESTYLE 26:PIN 1. CATHODE 2. ANODE 3. NO CONNECTIONSTYLE 27:PIN 1. CATHODE 2. CATHODE 3. 100 10T T3 XTOP VIEWSIDE VIEWEND : 28:PIN 1. ANODE 2. ANODE 3. ANODEMECHANICAL CASE OUTLINEPACKAGE DIMENSIONSON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other Semiconductor reserves the right to make changes without further notice to any products herein. ON Semiconductor makes no warranty, representation or guarantee regardingthe suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability arising out of the application or use of any product or circuit, and specificallydisclaims any and all liability, including without limitation special, consequential or incidental damages.


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